CY7B923
CY7B933
Transmitter Switching Characteristics Over the Operating Range[7]
7B923-155
Min. Max
7B923
7B923-400
Parameter
tCKW
tB
Description
Min.
30.3
Max
Min.
25
Max Unit
Write Clock Cycle
Bit Time[15]
62.5
6.25
6.5
66.7
6.67
62.5
62.5
6.25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
3.03 6.25
2.5
6.5
6.5
5
tCPWH
tCPWL
tSD
CKW Pulse Width HIGH
6.5
CKW Pulse Width LOW
6.5
6.5
Data Set-Up Time[16]
Data Hold Time[16]
5
5
tHD
0
0
6tB + 8
0
0
tSENP
tHENP
tPDR
tPPWH
tPDF
Enable Set-Up Time (to insure correct RP)[17]
Enable Hold Time (to insure correct RP)[17]
Read Pulse Rise Alignment[18]
Read Pulse HIGH[18]
6tB + 8
0
6tB + 8
0
–4
2
–4
2
–4
2
4tB–3
6tB–3
4tB–3
6tB–3
4tB–3
6tB–3
Read Pulse Fall Alignment[18]
tRISE
tFALL
tDJ
PECL Output Rise Time 20−80% (PECL Test Load)[13]
PECL Output Fall Time 80−20% (PECL Test Load)[13]
Deterministic Jitter (peak-peak)[13, 19]
Random Jitter (peak-peak)[13, 20]
Random Jitter (σ)[13, 20]
1.2
1.2
35
1.2
1.2
35
1.2
1.2
35
tRJ
175
20
175
20
175
20
tRJ
[7]
Receiver Switching Characteristics Over the Operating Range
7B933-155
7B933
7B933-400
Parameter
Description
Min.
Max
Min.
Max.
Min.
Max. Unit
tCKR
Read Clock Period (No Serial Data Input), REFCLK as
Reference[21]
–1
+1
–1
+1
–1
+1
%
tB
Bit Time[22]
6.25
5tB–3
5tB–3
tB–2.5
5tB–3
4tB–3
6.67
3.03
5tB–3
5tB–3
tB–2.5
5tB–3
4tB–3
6.25
2.5
6.25
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
tCPRH
tCPRL
tRH
Read Clock Pulse HIGH
Read Clock Pulse LOW
RDY Hold Time
5tB–3
5tB–3
tB–2.5
5tB–3
4tB–3
2tB–2
tB–2.5
2tB–3
–0.1
tPRF
tPRH
tA
RDY Pulse Fall to CKR Rise
RDY Pulse Width HIGH
Data Access Time[23, 24]
Data Hold Time[23, 24]
2tB–2 2tB+4 2tB–2
2tB+4
+0.1
2tB+4
+0.1
tROH
tH
tB–2.5
2tB–3
tB–2.5
2tB–3
–0.1
Data Hold Time from CKR Rise [23, 24]
tCKX
REFCLK Clock Period Referenced to CKW of Trans- –0.1
mitter[25]
+0.1
Notes:
15. Transmitter t is calculated as t
/10. The byte rate is one tenth of the bit rate.
B
CKW
16. Data includes D , SC/D, SVS, ENA, ENN, and BISTEN. t and t minimum timing assures correct data load on rising edge of CKW, but not RP function or timing.
0−7
SD
HD
17. t
and t
timing insures correct RP function and correct data load on the rising edge of CKW.
SENP
HENP
18. Loading on RP is the standard TTL test load shown in part (a) of AC Test Loads and Waveforms except C = 15 pF.
L
19. While sending continuous K28.5s, RP unloaded, outputs loaded to 50Ω to V −2.0V, over the operating range.
CC
20. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to CKW input, over the operating
range.
21. The period of t
will match the period of the transmitter CKW when the receiver is receiving serial data. When data is interrupted, CKR may drift to one of the range limits above.
CKR
22. Receiver t is calculated as t
/10 if no data is being received, or t
/10 if data is being received. See note.
B
CKR
CKW
23. Data includes Q , SC/D, and RVS.
0−7
24. t , t
, and t specifications are only valid if all outputs (CKR, RDY, Q , SC/D, and RVS) are loaded with similar DC and AC loads.
A
ROH
H
0
−
7
25. REFCLK has no phase or frequency relationship with CKR and only acts as a centering reference to reduce clock synchronization time. REFCLK must be within
0.1% of the transmitter CKW frequency, necessitating a ±500-PPM crystal.
Document #: 38-02017 Rev. *E
Page 28 of 33
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