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CY62136VLL-70ZI 参数 Datasheet PDF下载

CY62136VLL-70ZI图片预览
型号: CY62136VLL-70ZI
PDF下载: 下载PDF文件 查看货源
内容描述: 128K ×16静态RAM [128K x 16 Static RAM]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 12 页 / 221 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY62136V MoBL™
Switching Waveforms
(continued)
Read Cycle No. 2
[11, 12]
CE
t
ACE
OE
t
DOE
BHE/BLE
t
LZOE
t
HZBE
t
DBE
t
LZBE
DATA OUT
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
50%
I
SB
I
CC
DATA VALID
HIGH
IMPEDANCE
t
HZOE
t
RC
t
PD
t
HZCE
[8,
13, 14]
Write Cycle No. 1 (WE Controlled)
t
WC
ADDRESS
CE
t
AW
WE
t
SA
t
PWE
t
HA
BHE/BLE
t
BW
OE
t
SD
DATA I/O
NOTE
15
t
HZOE
Notes:
12. Address valid prior to or coincident with CE transition LOW.
13. Data I/O is high impedance if OE = V
IH
.
14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
15. During this period, the I/Os are in output state and input signals should not be applied.
t
HD
DATA VALID
IN
Document #: 38-05087 Rev. **
Page 6 of 12