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CY62136VLL-70ZI 参数 Datasheet PDF下载

CY62136VLL-70ZI图片预览
型号: CY62136VLL-70ZI
PDF下载: 下载PDF文件 查看货源
内容描述: 128K ×16静态RAM [128K x 16 Static RAM]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 12 页 / 221 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY62136V MoBL™
AC Test Loads and Waveforms
R1
V
CC
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
V
CC
OUTPUT
GND
5 pF
INCLUDING
JIG AND
SCOPE
R2
Rise Time:
1 V/ns
R1
V
CC
Typ
10%
ALL INPUT PULSES
90%
90%
10%
Fall Time:
1 V/ns
(a)
(b)
(c)
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
R1
R2
R
TH
V
TH
3.0V
1105
1550
645
1.75V
UNIT
Ohms
Ohms
Ohms
Volts
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
Description
V
CC
for Data Retention
Data Retention Current
V
CC
= 1.0V
CE > V
CC
0.3V,
V
IN
> V
CC
0.3V or
V
IN
< 0.3V
No input may exceed
V
CC
+0.3V
LL
Conditions
[5]
Min.
1.0
0.5
Typ.
[2]
Max.
3.6
7.5
Unit
V
µA
t
CDR[3]
t
R[4]
Chip Deselect to Data
Retention Time
Operation Recovery Time
0
70
ns
ns
Data Retention Waveform
DATA RETENTION MODE
V
CC
V
CC(min.)
t
CDR
V
DR
> 1.0 V
V
CC(min.)
t
R
CE
Notes:
4. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min)
>
100 ms or stable at V
CC(min)
>
100 ms.
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to V
CC
typ., and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
Document #: 38-05087 Rev. **
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