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CY62136VLL-70ZI 参数 Datasheet PDF下载

CY62136VLL-70ZI图片预览
型号: CY62136VLL-70ZI
PDF下载: 下载PDF文件 查看货源
内容描述: 128K ×16静态RAM [128K x 16 Static RAM]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 12 页 / 221 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY62136V MoBL™
Switching Characteristics
Over the Operating Range
[5]
55 ns
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
WRITE CYCLE
[8, 9]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
BLE / BHE LOW to Write End
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[6, 7]
WE HIGH to Low Z
[6]
70 ns
Max.
Min.
70
55
70
10
55
25
70
35
5
25
25
10
25
25
0
55
25
70
35
5
25
25
70
60
60
0
0
50
60
30
0
20
25
10
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[6]
OE HIGH to High Z
[6, 7]
CE LOW to Low Z
[6]
CE HIGH to High Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
BLE / BHE LOW to Data Valid
BLE / BHE LOW to Low Z
[6, 7]
BLE / BHE HIGH to High Z
[8]
Min.
55
10
5
10
0
5
55
45
45
0
0
40
50
25
0
5
Switching Waveforms
Read Cycle No. 1
[10,
11]
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
Notes:
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
10. Device is continuously selected. OE, CE = V
IL
.
11. WE is HIGH for read cycle.
Document #: 38-05087 Rev. **
Page 5 of 12