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CY37064VP100-143AC 参数 Datasheet PDF下载

CY37064VP100-143AC图片预览
型号: CY37064VP100-143AC
PDF下载: 下载PDF文件 查看货源
内容描述: 5V , 3.3V , ISR ™高性能的CPLD [5V, 3.3V, ISR⑩ High-Performance CPLDs]
分类和应用: 可编程逻辑器件输入元件时钟
文件页数/大小: 63 页 / 1784 K
品牌: CYPRESS [ CYPRESS ]
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Ultra37000 CPLD Family  
Switching Characteristics Over the Operating Range[12] (continued)  
Parameter  
Description  
Unit  
ns  
tWH  
tIS  
Clock or Latch Enable Input HIGH Time[8]  
Input Register or Latch Set-up Time  
Input Register or Latch Hold Time  
ns  
tIH  
ns  
[13, 14, 15]  
[13, 14, 15]  
tICO  
Input Register Clock or Latch Enable to Combinatorial Output  
Input Register Clock or Latch Enable to Output Through Transparent Output Latch  
ns  
tICOL  
ns  
Synchronous Clocking Parameters  
[14, 15]  
tCO  
Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output  
ns  
ns  
ns  
[13]  
tS  
Set-Up Time from Input to Sync. Clk (CLK0, CLK1, CLK2, or CLK3) or Latch Enable  
Register or Latch Data Hold Time  
tH  
[13, 14, 15]  
[13]  
tCO2  
Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Combinatorial Output ns  
Delay (Through Logic Array)  
tSCS  
Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output Synchronous ns  
Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable (Through Logic Array)  
[13]  
tSL  
tHL  
Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK0 ns  
CLK1, CLK2, or CLK3) or Latch Enable  
Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK0,  
CLK1, CLK2, or CLK3) or Latch Enable  
ns  
Product Term Clocking Parameters  
[13, 14, 15]  
tCOPT  
tSPT  
Product Term Clock or Latch Enable (PTCLK) to Output  
ns  
ns  
ns  
ns  
Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK)  
Register or Latch Data Hold Time  
tHPT  
[13]  
tISPT  
Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or  
Latch Enable (PTCLK)  
tIHPT  
Buried Register Used as an Input Register or Latch Data Hold Time  
ns  
ns  
[13, 14, 15]  
tCO2PT  
Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array)  
Pipelined Mode Parameters  
[13]  
tICS  
Input Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) to Output Register Synchronous ns  
Clock (CLK0, CLK1, CLK2, or CLK3)  
Operating Frequency Parameters  
fMAX1 Maximum Frequency with Internal Feedback (Lesser of 1/tSCS, 1/(tS + tH), or 1/tCO  
fMAX2 Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH),  
[5]  
)
MHz  
MHz  
[5]  
1/(tS + tH), or 1/tCO  
)
[5]  
fMAX3  
fMAX4  
Maximum Frequency with External Feedback (Lesser of 1/(tCO + tS) or 1/(tWL + tWH  
)
MHz  
Maximum Frequency in Pipelined Mode (Lesser of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH), MHz  
[5]  
or 1/tSCS  
)
Reset/Preset Parameters  
tRW  
Asynchronous Reset Width[5]  
ns  
ns  
ns  
ns  
ns  
ns  
[13]  
tRR  
Asynchronous Reset Recovery Time[5]  
Asynchronous Reset to Output  
Asynchronous Preset Width[5]  
[13, 14, 15]  
tRO  
tPW  
[13]  
tPR  
Asynchronous Preset Recovery Time[5]  
[13, 14, 15]  
tPO  
User Option Parameters  
Asynchronous Preset to Output  
tLP  
Low Power Adder  
ns  
ns  
ns  
tSLEW  
t3.3IO  
Slow Output Slew Rate Adder  
3.3V I/O Mode Timing Adder[5]  
Document #: 38-03007 Rev. *C  
Page 18 of 62  
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