Ultra37000 CPLD Family
AC Characteristics
3.3V AC Test Loads and Waveforms
295Ω (COM'L)
393Ω (MIL)
295Ω (COM’L)
393Ω (MIL)
ALL INPUT PULSES
3.3V
3.3V
3.0V
GND
90%
10%
90%
10%
OUTPUT
OUTPUT
340Ω (COM'L)
453Ω (MIL)
340Ω (COM’L)
453Ω (MIL)
35 pF
5 pF
<2 ns
<2 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
158Ω (COM’L)
270Ω (MIL)
1.77V (COM'L)
OUTPUT
1.77V (MIL)
5 OR 35 pF
Parameter[11]
VX
Output Waveform—Measurement Level
tER(–)
1.5V
VOH
0.5V
0.5V
VX
VX
tER(+)
tEA(+)
tEA(–)
2.6V
1.5V
Vthe
VOL
VOH
0.5V
VX
VX
0.5V
VOL
(d) Test Waveforms
Switching Characteristics Over the Operating Range[12]
Parameter
Description
Unit
Combinatorial Mode Parameters
[13, 14, 15]
tPD
Input to Combinatorial Output
ns
ns
ns
ns
ns
[13, 14, 15]
[13, 14, 15]
tPDL
Input to Output Through Transparent Input or Output Latch
Input to Output Through Transparent Input and Output Latches
Input to Output Enable
tPDLL
[13, 14, 15]
tEA
[11, 13]
tER
Input to Output Disable
Input Register Parameters
tWL
Clock or Latch Enable Input LOW Time[8]
ns
Notes:
11.
tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.
12. All AC parameters are measured with two outputs switching and 35-pF AC Test Load.
13. Logic Blocks operating in Low-Power Mode, add tLP to this spec.
14. Outputs using Slow Output Slew Rate, add tSLEW to this spec.
15. When VCCO = 3.3V, add t3.3IO to this spec.
Document #: 38-03007 Rev. *C
Page 17 of 62
CYPRESS [ CYPRESS ]
