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CY37064VP100-143AC 参数 Datasheet PDF下载

CY37064VP100-143AC图片预览
型号: CY37064VP100-143AC
PDF下载: 下载PDF文件 查看货源
内容描述: 5V , 3.3V , ISR ™高性能的CPLD [5V, 3.3V, ISR⑩ High-Performance CPLDs]
分类和应用: 可编程逻辑器件输入元件时钟
文件页数/大小: 63 页 / 1784 K
品牌: CYPRESS [ CYPRESS ]
 浏览型号CY37064VP100-143AC的Datasheet PDF文件第13页浏览型号CY37064VP100-143AC的Datasheet PDF文件第14页浏览型号CY37064VP100-143AC的Datasheet PDF文件第15页浏览型号CY37064VP100-143AC的Datasheet PDF文件第16页浏览型号CY37064VP100-143AC的Datasheet PDF文件第18页浏览型号CY37064VP100-143AC的Datasheet PDF文件第19页浏览型号CY37064VP100-143AC的Datasheet PDF文件第20页浏览型号CY37064VP100-143AC的Datasheet PDF文件第21页  
Ultra37000 CPLD Family  
AC Characteristics  
3.3V AC Test Loads and Waveforms  
295(COM'L)  
393(MIL)  
295(COM’L)  
393(MIL)  
ALL INPUT PULSES  
3.3V  
3.3V  
3.0V  
GND  
90%  
10%  
90%  
10%  
OUTPUT  
OUTPUT  
340(COM'L)  
453(MIL)  
340(COM’L)  
453(MIL)  
35 pF  
5 pF  
<2 ns  
<2 ns  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
(c)  
(a)  
(b)  
Equivalent to:  
THÉVENIN EQUIVALENT  
158(COM’L)  
270(MIL)  
1.77V (COM'L)  
OUTPUT  
1.77V (MIL)  
5 OR 35 pF  
Parameter[11]  
VX  
Output Waveform—Measurement Level  
tER(–)  
1.5V  
VOH  
0.5V  
0.5V  
VX  
VX  
tER(+)  
tEA(+)  
tEA(–)  
2.6V  
1.5V  
Vthe  
VOL  
VOH  
0.5V  
VX  
VX  
0.5V  
VOL  
(d) Test Waveforms  
Switching Characteristics Over the Operating Range[12]  
Parameter  
Description  
Unit  
Combinatorial Mode Parameters  
[13, 14, 15]  
tPD  
Input to Combinatorial Output  
ns  
ns  
ns  
ns  
ns  
[13, 14, 15]  
[13, 14, 15]  
tPDL  
Input to Output Through Transparent Input or Output Latch  
Input to Output Through Transparent Input and Output Latches  
Input to Output Enable  
tPDLL  
[13, 14, 15]  
tEA  
[11, 13]  
tER  
Input to Output Disable  
Input Register Parameters  
tWL  
Clock or Latch Enable Input LOW Time[8]  
ns  
Notes:  
11.  
tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.  
12. All AC parameters are measured with two outputs switching and 35-pF AC Test Load.  
13. Logic Blocks operating in Low-Power Mode, add tLP to this spec.  
14. Outputs using Slow Output Slew Rate, add tSLEW to this spec.  
15. When VCCO = 3.3V, add t3.3IO to this spec.  
Document #: 38-03007 Rev. *C  
Page 17 of 62  
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