PLC LV Evaluation Board
Table 3-5. J8 I2C Header Pins
J8 Pin Name
Description
The VDD pin can provide a maximum of 50 mA at 5 V to an external board. It is only
to source the current. Do not supply power to this pin for powering the CY8CPLC10
device. Note that the PWR jumper, as explained in the next section, needs to be
connected to enable this functionality.
V – Vdd
The Gnd pin can provide the ground reference to an external board. This pin con-
nects to the ground of the CY3273 board.
G – Gnd
The I2C data (SDA) pin is the data line for the I2C communication. This pin is
directly connected to the I2C_SDA pin on the CY8CPLC10 device. Check the next
D – I2C Data (SDA)
section for appropriate jumper settings for I2C communication through this pin.
The I2C clock (SCL) pin is the clock line for the I2C communication. This pin is
directly connected to the I2C_SCL pin on the CY8CPLC10 device. Check the next
C – I2C Clock (SCL)
section for appropriate jumper settings for I2C communication through this pin.
Connecting the reset of an external board to this pin enables the resetting of the
CY8CPLC10 device through the external board. Note that the RES jumper, as
explained in the next section, must be connected to enable this functionality.
R – Reset
2
Figure 3-6. I C Header for Communication
3.4.2
Setting Up Manual Addressing on PLC Boards
The PLC evaluation board contains a five-position DIP switch. The first three switches S2[3-5] are
used to manually set a logical address for the PLC chip. Logical addresses for up to eight nodes can
be set up using these DIP switches.
S2[3] is the MSB. S2[5] is the LSB. Set the DIP switch to the ON position for the particular bit to be
logic ‘1’ and OFF position for it to be logic ‘0’. For example, for setting the logical address of 0X06
(see Figure 3-7):
S2[5] → OFF = 0
S2[4] → ON = 1
S2[3] → ON = 1
24
CY3273 Cypress Low Voltage Powerline Communication Evaluation Kit Guide, Doc. # 001-55382 Rev. *C
[+] Feedback
CYPRESS [ CYPRESS ]
