CY2310ANZPVC-1 参数 Datasheet PDF下载

CY7C138

CY7C139

Switching Waveforms

(continued)

Timing Diagram of Semaphore Contention

[26, 27, 28]

A

0L

–A

2L

MATCH

R/W

L

SEM

L

t

SPS

A

0R

–A

2R

MATCH

R/W

R

SEM

R

C138-14

Timing Diagram of Read with BUSY (M/S=HIGH)

ADDRESS

R

R/W

R

[20]

t

WC

MATCH

t

PWE

t

SD

DATA IN

R

t

PS

ADDRESS

L

MATCH

t

BLA

BUSY

L

t

DDD

DATA

OUTL

t

WDD

VALID

t

HD

t

BHA

t

BDD

VALID

C138-15

Write Timing with Busy Input (M/S=LOW)

R/W

t

WB

t

PWE

BUSY

t

WH

C138-16

Notes:

26. I/O

0R

= I/O

0L

= LOW (request semaphore); CE

R

= CE

L

= HIGH

27. Semaphores are reset (available to both ports) at cycle start.

28. If t

SPS

is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.

9