CY7C138
CY7C139
Switching Characteristics
Over the Operating Range
[8]
7C138-15
7C139-15
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE[9,10,11]
t
HZOE[9,10,11]
t
LZCE[9,10,11]
t
HZCE[9,10,11]
t
PU[11]
t
PD[11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE[10,11]
t
LZWE[10,11]
t
WDD[12]
t
DDD[12]
t
BLA
t
BHA
t
BLC
t
BHC
t
PS
t
WB
t
WH
t
BDD[14]
Read Cycle Time
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
0
15
3
10
0
25
3
10
3
15
0
35
3
15
10
3
15
3
20
0
55
15
15
3
25
15
3
20
3
25
25
25
3
35
20
3
25
35
35
3
55
25
55
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C138-25
7C139-25
Min.
Max.
7C138-35
7C139-35
Min.
Max.
7C138-55
7C139-55
Min.
Max.
Unit
WRITE CYCLE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold From Write End
Address Set-Up to Write Start
Write Pulse Width
Data Set-Up to Write End
Data Hold From Write End
R/W LOW to High Z
R/W HIGH to Low Z
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
3
30
25
15
12
12
2
0
12
10
0
10
3
50
30
25
20
20
2
0
20
15
0
15
3
60
35
35
30
30
2
0
25
15
0
20
3
70
40
55
40
40
2
0
30
20
0
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
BUSY TIMING
[13]
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set-Up for Priority
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
BUSY HIGH to Data Valid
5
0
13
Note
13
15
15
15
15
5
0
20
Note
13
20
20
20
20
5
0
30
Note
13
20
20
20
20
5
0
40
Note
13
45
40
40
35
ns
ns
ns
ns
ns
ns
ns
ns
INTERRUPT TIMING
[13]
t
INS
t
INR
INT Set Time
INT Reset Time
15
15
25
25
25
25
30
30
ns
ns
5
CYPRESS [ CYPRESS SEMICONDUCTOR ]
