CY2305
CY2309
Table 2. Pin Description for CY2309
Pin
13
14
15
16
V
DD
CLKA3
CLKA4
CLKOUT
Signal
3.3V supply
Buffered clock output, Bank A
Buffered clock output, Bank A
Buffered output, internal feedback on this pin
Description
Select Input Decoding for CY2309
S2
0
0
1
1
S1
0
1
0
1
CLOCK A1–A4
Three-state
Driven
Driven
Driven
CLOCK B1–B4
Three-state
Three-state
Driven
Driven
CLKOUT
Driven
Driven
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shutdown
N
N
Y
N
Figure 3. REF. Input to CLKA/CLKB Delay vs. Loading Difference between CLKOUT and CLKA/CLKB Pins
Zero Delay and Skew Control
All outputs must be uniformly loaded to achieve Zero Delay between the input and output. Since the CLKOUT pin is the internal
feedback to the PLL, its relative loading can adjust the input-output delay. This is shown in the above graph.
For applications requiring zero input-output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not
used, it must have a capacitive load, equal to that on other outputs, for obtaining zero input-output delay. If input to output delay
adjustments are required, use the above graph to calculate loading differences between the CLKOUT pin and other outputs.
For zero output-output skew, be sure to load all outputs equally. For further information refer to the application note entitled “CY2305
and CY2309 as PCI and SDRAM Buffers.”
Notes
4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
Document #: 38-07140 Rev. *I
Page 3 of 15
CYPRESS [ CYPRESS SEMICONDUCTOR ]
