CY2305
CY2309
Pinouts
Figure 1. Pin Diagram - CY2305
REF
CLK2
CLK1
GND
1
2
3
4
8
7
6
5
CLKOUT
CLK4
V
DD
CLK3
Table 1. Pin Description for CY2305
Pin
1
2
3
4
5
6
7
8
REF
CLK2
CLK1
GND
CLK3
V
DD
CLK4
CLKOUT
Signal
Buffered clock output
Buffered clock output
Ground
Buffered clock output
3.3V supply
Buffered clock output
Buffered clock output, internal feedback on this pin
Description
Input reference frequency, 5V-tolerant input
Figure 2. Pin Diagram - CY2309
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLKOUT
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
Table 2. Pin Description for CY2309
Pin
1
2
3
4
5
6
7
8
9
10
11
12
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
S1
CLKB3
CLKB4
GND
Signal
Buffered clock output, Bank A
Buffered clock output, Bank A
3.3V supply
Ground
Buffered clock output, Bank B
Buffered clock output, Bank B
Select input, bit 2
Select input, bit 1
Buffered clock output, Bank B
Buffered clock output, Bank B
Ground
Description
Input reference frequency, 5V-tolerant input
Notes
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
Document #: 38-07140 Rev. *I
Page 2 of 15
CYPRESS [ CYPRESS SEMICONDUCTOR ]
