CG5982AF
Switching Characteristics
Over the Operating Range
[4, 9]
(continued)
CG5982AF
Parameter
t
HZOE
t
HZCE
t
PU
t
PD
Write Cycle
[13]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Busy/Interrupt Timing
t
BLA
t
BHA
t
BLC
t
BHC
t
PS
t
WB
t
WH
t
BDD
t
DDD
t
WDD
Interrupt Timing
[15]
t
WINS
t
EINS
t
INS
t
OINR
t
EINR
t
INR
R/W to INTERRUPT Set Time
CE to INTERRUPT Set Time
Address to INTERRUPT Set Time
OE to INTERRUPT Reset Time
[14]
CE to INTERRUPT Reset Time
[14]
Address to INTERRUPT Reset Time
[14]
45
45
45
45
45
45
ns
ns
ns
ns
ns
ns
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
[14]
BUSY LOW from CE LOW
BUSY HIGH from CE
HIGH
[14]
5
0
35
45
Note 15
Note 15
Port Set-up for Priority
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
BUSY HIGH to Valid Data
Write Data Valid to Read Data Valid
Write Pulse to Data Delay
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
R/W Pulse Width
Data Set-up to Write End
Data Hold from Write End
R/W LOW to High-Z
[8]
R/W HIGH to Low-Z
[8]
0
55
40
40
2
0
30
20
0
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OE HIGH to
High-Z
[8, 11, 12]
0
35
CE HIGH to High-Z
[8, 11, 12]
CE LOW to Power-Up
[8]
CE HIGH to Power-Down
[8]
Description
Min.
Max.
25
25
Unit
ns
ns
ns
ns
Notes:
12. t
LZCE
, t
LZWE
, t
HZOE
, t
LZOE,
t
HZCE,
and t
HZWE
are tested with C
L
= 5 pF, as in (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
13. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
14. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
15. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
Document #: 38-06067 Rev. *C
Page 4 of 12
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