CG5982AF
Switching Characteristics Over the Operating Range[4, 9] (continued)
CG5982AF
Parameter
Description
Min.
Max.
Unit
ns
tHZOE
tHZCE
tPU
OE HIGH to High-Z[8, 11, 12]
CE HIGH to High-Z[8, 11, 12]
CE LOW to Power-Up[8]
25
25
ns
0
ns
tPD
CE HIGH to Power-Down[8]
35
ns
Write Cycle[13]
tWC
Write Cycle Time
55
40
40
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE LOW to Write End
Address Set-up to Write End
tAW
tHA
Address Hold from Write End
Address Set-up to Write Start
R/W Pulse Width
tSA
0
tPWE
30
20
0
tSD
Data Set-up to Write End
Data Hold from Write End
R/W LOW to High-Z [8]
R/W HIGH to Low-Z [8]
tHD
tHZWE
25
tLZWE
0
Busy/Interrupt Timing
tBLA
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch[14]
BUSY LOW from CE LOW
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBHA
tBLC
tBHC
BUSY HIGH from CE HIGH[14]
tPS
Port Set-up for Priority
5
0
tWB
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
BUSY HIGH to Valid Data
tWH
35
tBDD
45
tDDD
Write Data Valid to Read Data Valid
Write Pulse to Data Delay
Note 15
Note 15
tWDD
Interrupt Timing[15]
tWINS
tEINS
tINS
R/W to INTERRUPT Set Time
45
45
45
45
45
45
ns
ns
ns
ns
ns
ns
CE to INTERRUPT Set Time
Address to INTERRUPT Set Time
OE to INTERRUPT Reset Time[14]
CE to INTERRUPT Reset Time[14]
Address to INTERRUPT Reset Time[14]
tOINR
tEINR
tINR
Notes:
12. t
, t
, t
, t
t
and t
are tested with C = 5 pF, as in (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
HZWE L
LZCE LZWE HZOE LZOE, HZCE,
13. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
14. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
15. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
Document #: 38-06067 Rev. *C
Page 4 of 12
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