CG5982AF
Switching Waveforms (continued)
Write Cycle No.1 (OE Three-States Data I/Os—Either Port)[13, 19]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
R/W
t
t
HD
SD
DATAIN
OE
DATA VALID
t
HZOE
HIGH IMPEDANCE
DOUT
Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)[13, 20]
t
WC
ADDRESS
CE
t
t
SCE
HA
t
AW
t
SA
t
PWE
R/W
t
t
HD
SD
DATAIN
DATA VALID
t
t
LZWE
HZWE
HIGH IMPEDANCE
DOUT
Notes:
19. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
or t
+ t to allow the data I/O pins to enter high impedance
SD
PWE
HZWE
and for data to be placed on the bus for the required t
.
SD
20. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high-impedance state.
Document #: 38-06067 Rev. *C
Page 6 of 12
[+] Feedback
CYPRESS [ CYPRESS ]
