CG5982AF
Switching Waveforms
(continued)
Write Cycle No.1 (OE Three-States Data I/Os—Either Port)
[13, 19]
t
WC
ADDRESS
t
SCE
CE
t
SA
R/W
t
SD
DATA
IN
DATA VALID
t
HD
t
AW
t
HA
t
PWE
OE
t
HZOE
HIGH IMPEDANCE
D
OUT
Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)
[13, 20]
t
WC
ADDRESS
t
SCE
CE
t
SA
R/W
t
SD
DATA
IN
t
HZWE
D
OUT
Notes:
19. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
PWE
or t
HZWE
+ t
SD
to allow the data I/O pins to enter high impedance
and for data to be placed on the bus for the required t
SD
.
20. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high-impedance state.
t
HA
t
AW
t
PWE
t
HD
DATA VALID
t
LZWE
HIGH IMPEDANCE
Document #: 38-06067 Rev. *C
Page 6 of 12
CYPRESS [ CYPRESS SEMICONDUCTOR ]
