PRELIMINARY
C9926
Low EMI Clock Generator for Intel 133MHz/ 2DIMM Chipset Systems
133MHz Host
100MHz Host
66MHz Host
Symbol
Parameter
Units
Min
Max
Min
69.8413
1.0
Max
71.0
4.0
Min
69.8413
1.0
Max
71.0
4.0
Tperiod
Tr / Tf
REF period1,2
69.8413
71.0
4.0
ns
ns
ps
ns
ms
%
REF rise and fall times3
REF Cycle to Cycle Jitter2
Output enable delay (all outputs) 4
All clock Stabilization from power-up8
Duty Cycle for All outputs9
1.0
-
TCCJ
-
1000
10.0
3
-
1000
10.0
3
1000
10.0
3
TpZL, tpZH
tstable
1.0
1.0
1.0
Tduty
45
55
45
55
45
55
Note 1: This parameter is measured as an average over 1us duration, with a crystal center frequency of 14.31818MHz
Note 2: All outputs loaded as per table 5, Probes are placed on the pins and taken at 1.5V levels for 3.3V signals and at 1.25V for
2.5V signals (figs. 10A and 10B).
Note 3: Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V
and 2.0V for 2.5V signals (see Fig.10A and Fig.10B)
Note 4: Measured from when TS#/PD# is switched to high (enable).
Note 5: This measurement is applicable with Spread ON or Spread OFF.
Note 6: Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals, (see
Figs. 10A & 10B)
Note 7: Probes are placed on the pins, and measurements are acquired at 0.4V.
Note 8: The time specified is measured from when all VDD’s reach their respective supply rail (3.3V and 2.5V) till the frequency
output is stable and operating within the specifications
Note 9: Device designed for Typical Duty Cycle of 50%.
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07070 Rev. **
5/4/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress
Page 17 of 21
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