PRELIMINARY
C9926
Low EMI Clock Generator for Intel 133MHz/ 2DIMM Chipset Systems
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
Maximum Ratings
Maximum Input Voltage Relative to VSS: VSS - 0.3V
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Maximum Input Voltage Relative to VDD: VDD + 0.3V
Storage Temperature:
Operating Temperature:
-65°C to + 150°C
0°C to +85°C
Maximum ESD protection
Maximum Power Supply:
2KV
5.5V
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD)
.
DC Parameters
Characteristic
Symbol Min
Typ
Max
1.0
Units
V
Conditions
Input Low Voltage
VIL1
VIH1
VIL2
VIH2
IIL1
-
-
-
-
-
Note 1
Input High Voltage
2.0
-
1.0
-
V
Input Low Voltage
-
V
Note 2
Input High Voltage
2.2
V
Input Low Current (@VIL = VSS)
Input High Current (@VIL =VDD)
Input Low Current (@VIL = VSS)
Input High Current (@VIL =VDD)
Tri-State leakage Current
Dynamic Supply Current
Dynamic Supply Current
Static Supply Current
Input pin capacitance
Output pin capacitance
Pin inductance
-66
-5
µA
µA
µA
µA
µA
mA
mA
mA
pF
pF
nH
pF
V
For internal Pull up resistors,
Notes 1,3
IIH1
-5
5
IIL2
-5
5
For internal Pull Down resistor
Note 4
IIH2
5
66
10
360
100
10
5
Ioz
-
-
TS# = SEL0 = 0, Vo = VDD or VSS
SEL(3:0) = 0001
Idd3.3V
Idd2.5V
Isdd
-
-
-
-
SEL(3:0) = 0001
-
-
PD# = 0. SEL(3:0) = X
Cin
-
-
Cout
Lpin
-
-
6
-
-
34
7
Crystal pin capacitance
Crystal DC Bias Voltage
Crystal Startup time
Cxtal
VBIAS
Txs
32
0.3Vdd
-
38
0.7Vdd
40
Measured from Pin to Ground. Note 5
From Stable 3.3V power supply.
Vdd/2
-
µs
VDD=VDDS = 3.3V ±5%, VDDC = VDDI = 2.5 ± 5%, TA = 0º to +70ºC
Applicable to input signals: SEL(0:3), TS#/PD#
Applicable to Sdata, and SCLK.
Although internal pull-up resistors have a typical value of 250K, this value may vary between 200K and 500K.
Although internal pull-down resistor has a typical value of 50K, this value may vary between 30K and 70K.
Although the device will reliably interface with crystals of a 17pF – 20pF CL range, it is optimized to interface with a typical CL = 18pF
crystal specifications.
Note1:
Note2:
Note3:
Note4:
Note5:
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07070 Rev. **
5/4/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress
Page 13 of 21
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