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C9837AT 参数 Datasheet PDF下载

C9837AT图片预览
型号: C9837AT
PDF下载: 下载PDF文件 查看货源
内容描述: [Processor Specific Clock Generator, CMOS, PDSO48, TSSOP-48]
分类和应用: 光电二极管外围集成电路
文件页数/大小: 20 页 / 319 K
品牌: CYPRESS [ CYPRESS ]
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+/+…when timing is critical  
C9837  
Low EMI Clock Generator for Intel Mobile 133MHz/2 SO-DIMM Chipset Systems  
Preliminary  
Expanded Frequency Selection (MHz) 1,2  
TEST  
ESEL ESEL SEL  
SEL  
0
CPU  
(0,1)  
66.7  
100  
133.3  
133.3  
70  
105  
140  
140  
73.3  
110  
146.7  
146.7  
80  
120  
160  
SDRAM  
(0:3), DCLK  
100*  
3V66  
(0:2)  
66.6  
66.6  
66.6  
66.6  
70  
70  
70  
70  
73.3  
73.3  
73.3  
73.3  
80  
80  
80  
80  
PCI_F,  
PCI(1:6)  
33  
Notes  
#
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
10  
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0% extension  
(Default)  
100*  
133.3  
100*  
105*  
105*  
140  
105*  
110*  
110*  
146.7  
110*  
120*  
120*  
160  
33  
33  
33  
35  
35  
35  
35  
36.6  
36.6  
36.6  
36.6  
40  
40  
40  
40  
5% extension  
10% extension  
20% extension  
160  
120*  
Note 1: Extended frequencies are only available via I2C interface. They are accessable via I2C Byte 5 bits 0,1.  
Note 2: 48M_DOT clock is constant at 48MHz and REF is constant at 14.31818MHz for all table selections.  
* Will be set to 133MHz and boosted accordingly, when Byte 3 Bit0 is set to logic 1.  
Table 2  
Power Management Functions  
Power Management on this device is controlled by the PD#, CPU_STP# and PCI_STP# pins. When PD# is high  
(default) the device is in normal running mode and all signals are active.  
The PD# signal is used to bring all clocks to a low level in an orderly fashion prior to power (all except AVDD) being  
removed from the part. When PD# is asserted (forced) low, the device transitions to a shutdown (power down) mode  
and all power supplies (3.3V and 2.5V except for AVDD) may then be removed. When PD# is sampled low by two  
consecutive rising edges of CPU clock, then all affected clocks are stopped in a low state on their next high-to-low  
transition. The REF and USB clocks are stopped in a low state as soon as possible. When in power down (and before  
power is removed), all outputs are synchronously stopped in a low state (see Figure 1 below), all PLL’s are shut off, and  
the crystal oscillator is disabled. When the device is shutdown, the I²C function is also disabled.  
At power up, using the PD# select pin, all clocks are started in such a manner as to guarantee a glitch free operation, no  
partial clock pulses.  
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,  
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571  
http://www.imicorp.com  
Rev 1.0  
3/30/2000  
Page 3 of 20  
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