+/+…when timing is critical
C9837
Low EMI Clock Generator for Intel Mobile 133MHz/2 SO-DIMM Chipset Systems
Preliminary
Pin Description
PIN
NAME
PWR
TYPE
DESCRIPTION
48
VDD
PU
Power-on Bi-directional Input / Output. At power-up, SEL0 is the input. When
the power supply voltage crosses the input threshold voltage, REF becomes the
output. See frequency Table for SEL0 selections.
SEL0/REF
2
3
Oscillator buffer input. Connect to a crystal or to an external clock.
Oscillator buffer output. Connect to a crystal. Do not connect when an external
clock is applied at XIN.
XIN
XOUT
41, 43
6, 7, 8
11
VDDC
VDD
VDDP
2.5V Host bus clock outputs
3.3V Fixed 66.6MHz clock outputs
Power-on Bi-directional Input / Output. At power-up, SEL1 is the input. When
the power supply voltage crosses the input threshold voltage, PCI_F becomes a
free running PCI clock. This clock continues to run when PCI_STP# is at a logic
low level. See frequency Table for SEL1 selections.
CPU(1,0)
3V66(0:2)
SEL1/PCI_F
PU
12, 14, 15, 17,
18, 19
VDDP
VDD
3.3V PCI clock outputs. These clocks synchronously stop in a low state when
PCI_STP# is brought to a logic low level. They synchronously resume running
when PCI_STP# is brought to a logic high state.
PCI (1:6)
23, 24
30
3.3V Fixed 48MHz clock outputs
48M(0,1)
CPU_STP#
CPU0 stop clock control input. When this signal is at a logic low level (0), CPU0
clock stops at a logic low level. Using this pin to start and stop CPU0 clock
insures synchronous (no short or long clocks) transitioning of this clock.
PCI stop clock control input. When this signal is at a logic low level (0), all PCI
clocks (except PCI_F) stop at a logic low level. Using this pin to start and stop
PCI clocks insures synchronous (no short or long clocks) transitioning of these
clocks. This pin has no effect on the PCI_F clock.
10
26
PCI_STP#
SDATA
Serial data input pin. Conforms to the Philips I2C specification of a Slave
Receive/Transmit device. This pin is an input when receiving data. It is an open
drain output when acknowledging or transmitting data. See I2C function
description.
27
28
Serial clock input pin. Conforms to the Philips I2C specification. See I2C
function description.
SCLK
PD#
PU
3.3V LVTTL compatible input. When held LOW, the device enters a power down
mode. This pin has an Internal Pull-Up. See power management function.
3.3V LVTTL compatible input for selecting test mode. See Table 1.
3.3V SDRAM feedback clock output. See Table1 for frequency selection. See
figure 4 for timing relationship.
29
32
TEST#
DCLK
VDDS
34, 35, 37, 38
45, 46
42
VDDS
VDDI
3.3V SDRAM clock outputs
2.5V IOAPIC clock outputs. See figure 4 for timing relationships.
2.5V Power for CPU clock output buffers
SDRAM(3:0)
IOAPIC(1,0)
VDDC
31, 36
16
3.3V Power for SDRAM and DCLK clock output buffers
3.3V Power for PCI clock output buffers
VDDS
VDDP
44
2.5V Power for IOAPIC clock output buffers
VDDI
20
3.3V Analog Power Supply
AVDD
1, 9, 25
3.3V Common Power Supply
VDD
4, 5, 13, 21, 22,
33, 39, 40, 47
Common Ground pins.
VSS
A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin. If these bypass capacitors
are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
PU = Internal Pull-Up. Typically 350k (range 200k to 500k).
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
http://www.imicorp.com
Rev 1.0
3/30/2000
Page 2 of 20
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