+/+…when timing is critical
C9837
Low EMI Clock Generator for Intel Mobile 133MHz/2 SO-DIMM Chipset Systems
Preliminary
Group Timing Relationships and Tolerances
CPU = 66.6MHz, SDRAM = 100MHz
Offset (ns)
Tolerance (ps)
Conditions
CPU to SDRAM/DCLK
CPU to 3V66
2.5
7.5
500
500
500
500
1000
N/A
180 degrees phase shift
When rising edges line-up
3V66 leads
SDRAM/DCLK to 3V66
3V66 to PCI
0
1.5-3.5
0
PCI to IOAPIC
48M(0,1)
Async
CPU = 100MHz, SDRAM = 100MHz
Offset (ns)
Tolerance (ps)
Conditions
CPU to SDRAM/DCLK
CPU to 3V66
5
500
500
500
500
1000
N/A
180 degrees phase shift
CPU leads
5
0
SDRAM/DCLK to 3V66
3V66 to PCI
When rising edges line-up
3V66 leads
1.5-3.5
0
PCI to IOAPIC
48M(0,1)
Async
CPU = 133.3MHz, SDRAM = 100MHz
Offset (ns)
Tolerance (ps)
Conditions
CPU to SDRAM/DCLK
CPU to 3V66
0
500
500
500
500
1000
N/A
When rising edges line-up
0
0
SDRAM/DCLK to 3V66
3V66 to PCI
When rising edges line-up
3V66 leads
1.5-3.5
0
PCI to IOAPIC
48M(0,1)
Async
CPU = 133.3MHz, SDRAM = 133.3MHz
Offset (ns)
3.75
Tolerance (ps)
Conditions
CPU to SDRAM/DCLK
CPU to 3V66
500
500
500
500
1000
180 degrees phase shift
0
SDRAM/DCLK to 3V66
3V66 to PCI
3.75
1.5-3.5
0
3V66 leads
PCI to IOAPIC
48M(0,1)
Async
N/A
Table 4
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
http://www.imicorp.com
Rev 1.0
3/30/2000
Page 8 of 20
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