C9830
133 MHz Clock Generator for Intel
®
820 Chipset
Preliminary
Pin Description
PIN No.
1, 45, 46
2
4
5
7
Pin Name
IOAPIC
(2:0)
HDREF
XIN
XOUT
PCI0/S2
PWR
VDDIO
VDD
VDD
VDD
I/O
O
O
I
O
I/O
Type
Description
2.5V clock outputs synchronous to the CPU clocks. See table1
High Drive buffered output of the reference signal applied at
Xin.
14.318MHz Crystal input
14.318MHz Crystal output
This is a bi-directional pin. See Application Note for input
strapping. When it is an input, this pin functions as part of the
frequency selection address,S2 (see Table 1). When it is an
output, it functions as a PCI0 clock output.
This is a bi-directional pin. See Application Note for input
strapping. When this pin is an input, it functions as part of the
frequency selection address,S1 (see Table 1). When it is an
output, it functions as a PCI1 clock output.
3.3V PCI clock outputs. Synchronous to CPU clocks.
3.3V AGP clock outputs. Synchronous to CPU clocks
Input strapping pin for frequency selection. (See table 1) This
pin is strapped at power on. Varying the state of this pin after
power up will not affect this device.
This is a bi-directional pin. See Application Note for input
strapping. When this pin is an input, it functions as part of the
frequency selection address, S1 (see Table 1). When it is an
output, it is a 48MHz USB clock output.
This is a bi-directional pin. See Application Note for input
strapping. When this pin is an input, it functions as a SIO select
pin for selecting the clock frequency at this same pin.
If SIO is strapped high, then output = 24MHz.
If SIO is strapped low, then output = 48MHz.
Serial data input pin. Conforms to the Philips I²C specification
of a Slave Receiver device. This pin is an input when receiving
data. It is an open drain output when acknowledging. See I²C
function description.
Serial clock input pin. Conforms to the Philips I²C 100KHz
Specs.
When this input pin is asserted low, the device is in Power
Down mode; all outputs are held low, and internal PLL’s are
shutoff.
2.5V Clock output, synchronous to CPU clocks. Drives the
DRCG. See table 1 for frequency selection.
2.5V CPU clock outputs. See Table 1 for frequency selection.
PU
8
PCI1/S1
I/O
PU
10,11,12,13,
15,16,18,19
21, 22, 23
25
PCI (2:9)
3V66 (0:2)
Sel133/100#
VDD
VDD
VDD
O
O
I
27
48MHz/S0
I/O
PU
28
SIO/
24_48# MHz
I/O
PU
34
SDATA
VDD
I
30
31
SCLK
PD#
VDD
VDD
I
I
42
35, 36, 39
CPU/2
CPU(0:2)
VDD
O
O
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST
MILPITAS, CA 95035, USA TEL: 408-263-6300. FAX 408-263-6571
http://www.imicorp.com/
Rev 1.1
4/25/2000
Page 2 of 14
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