C9830
133 MHz Clock Generator for Intel
®
820 Chipset
Preliminary
Serial Control Registers
NOTE:
The Pin # column lists the affected pin number where applicable. The @Pup column gives the state at true
power up. Bytes are set to the values shown only on true power up.
Following the acknowledge of the Address Byte, two additional bytes must be sent:
1) “Command
Code
“ byte, and
2) “Byte
Count”
byte. Must be programmed to FF for correct operation.
Although the data (bits) in these two bytes are considered “don’t care”, they must be sent and will be acknowledged.
After the Command Code and the Count bytes have been acknowledged, the below described sequence (Byte 0, Byte 1,
Byte2, ....) will be valid and acknowledged.
Byte 0: CPU Clock Register
(1 = Enable, 0 = Stopped)
Bit
7
6
5
4
3
@Pup
0
0
0
0
0
Pin#
25
7
8
27
-
Pin Description
1 = 133MHz CPU, 0 = 100 MHz CPU
S2, See Frequency Table
S1, See Frequency Table
S0, See Frequency Table
Frequency Selection = 0 then
frequency is selected by hardware,
pins 7, 8, 27
Frequency Selection = 1 then
frequency is selected via Byte0, bits
6:4
(Reserved)
See Select Function Table
See Select Function Table
Byte 2: PCI Clock Register
(1=Enable, 0=Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Pin#
16
15
13
12
11
10
8
7
Pin Description
PCI7
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
2
1
0
0
0
0
-
-
-
Byte 3: Control Register
(1=Enable, 0=Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
0
1
1
1
0
0
1
1
Pin#
-
23
22
21
-
-
19
18
Pin Description
Reserved
3V66_2
3V66_1
3V66_0
Reserved
Reserved
PCI9
PCI8
Select Function Table for Data Byte 0, Bits 0:1
Input
Conditions
Output Conditions
Byte 0
CPU
PCI
HDREF
IOAPIC
48/24M
(0:2)
(0:9)
(0:2)
Function
Bit 1
Bit 0
Normal
0
0
Note 1
Note 1
14.318M
Note 1
48/24M
Test
0
1
Test Mode – Follow the Selection Ratios
Spread
1
0
±
±
14.318M
±
48/24M
Spectrum
0.25%
0.25%
0.25%
Tristate
1
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Note 1: CPU, and PCI frequency selections are listed in Frequency Table.
Note 2: In Test Mode, the 48/24M clock outputs are: ÷2 for 48M output, ÷4 for
24M output
Byte 4: Control Register
(1=Enable, 0=Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
0
1
1
1
0
0
0
1
Pin#
-
1
45
46
-
-
-
2
Pin Description
Reserved
IOAPIC2
IOAPIC1
IOAPIC0
Reserved
Reserved
Reserved
HDREF
Byte 1: Clock Register
(1 = Enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
0
1
0
1
1
1
Pin#
27
28
-
42
-
39
36
35
Pin Description
48M
24/48M
Reserved
CPU/2
Reserved
CPU2
CPU1
CPU0
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST
MILPITAS, CA 95035, USA TEL: 408-263-6300. FAX 408-263-6571
http://www.imicorp.com/
Rev 1.1
4/25/2000
Page 6 of 14
CYPRESS [ CYPRESS SEMICONDUCTOR ]
