Approved Product
C9827H
High Performance Pentium® 4 Clock Synthesizer
AC Parameters
66 MHz
100 MHz
133 MHz
200 MHz
Symbol
TDC
TPeriod
Parameter
Xin Duty Cycle
Xin period
Units
%
nS
Notes
1, 11, 14
1, 2, 4, 11
Min
47.5
69.841
Max
52.5
71.0
Min
47.5
69.841
Max
52.5
71.0
Min
47.5
69.841
Max
52.5
71.0
Min
47.5
69.841
Max
52.5
71.0
VHIGH
VLOW
Tr / Tf
Xin High Voltage
Xin Low Voltage
Xin rise and fall
times
.7Vdd
0
-
Vdd
.3Vdd
10.0
.7Vdd
0
-
Vdd
.3Vdd
10.0
.7Vdd
0
-
Vdd
.3Vdd
10.0
.7Vdd
0
-
Vdd
.3Vdd
10.0
Volts
Volts
nS
13
TCCJ
Xin Cycle to Cycle
Jitter
-
500
-
500
-
500
-
-
500
pS
2, 5, 11
CPU at 0.7 Volts Timing
TSKEW
TCCJ
Any CPU to CPU
clock Skew
CPU Cycle to
Cycle Jitter
CPU and CPU#
Duty Cycle
CPU and CPU#
period
-
-
100
150
55
-
-
100
150
55
-
100
150
55
100
150
55
pS
pS
%
2, 5, 17
2, 17, 22
5, 17, 22
5, 17, 22
5, 6, 25
-
TDC
45
45
45
45
TPeriod
Tr / Tf
14.85
175
15.3
700
9.85
175
10.2
700
7.35
175
7.65
700
4.85
175
5.1
700
nS
ps
CPU and CPU#
rise and fall times
Rise.Fall Matching
Rise Time Variation
Fall Time Variation
crossing point
-
-
-
20%
125
125
430
-
-
-
20%
125
125
430
20%
125
125
430
-
20%
125
125
430
-
6, 21, 22
6, 22
6, 22
DeltaTr
DeltaTf
Vcross
-
-
ps
ps
mV
-
280
280
280
280
5, 22
voltage at 0.7 V
swing
CPU at 1.0 Volts Timing
TSKEW
TCCJ
Any CPU to any
CPU clock Skew
CPU Cycle to
Cycle Jitter
CPU and CPU#
Duty Cycle
-
-
100
150
55
-
-
100
150
55
-
100
150
55
-
100
150
55
pS
pS
%
2, 5, 17
2, 17
5, 17
5, 17
5, 25
7, 26
-
TDC
45
45
45
45
TPeriod
CPU and CPU#
period
14.85
175
15.3
467
325
9.85
175
10.2
467
325
7.35
175
7.65
467
325
4.85
175
5.1
467
325
nS
ps
ps
Differential
Tr / Tf
SE-
DeltaSlew
CPU and CPU#
rise and fall times
Absolute Single-
ended rise/fall
waveform
symmetry
Vcross
Cross point at 1.0
Volt swing
510
760
510
760
510
760
510
760
mV
26
TDC
TPeriod
THIGH
TLOW
Tr / Tf
3V66 Duty Cycle
3V66 period
3V66 high time
3V66 low time
3V66 rise and fall
times
45
55
15.3
-
45
55
15.3
-
45
55
15.3
-
45
55
15.3
-
%
2, 4
1, 2, 4
19
20
3
15.0
4.95
4.55
0.5
15.0
4.95
4.55
0.5
15.0
4.95
4.55
0.5
15.0
4.95
4.55
0.5
nS
nS
nS
nS
-
-
-
-
2.0
2.0
2.0
2.0
Tskew
Unbuffered
Tskew
Buffered
TCCJ
3V66 to 3V66 clock
skew
3V66 to 3V66 clock
skew
DRCG Cycle to
Cycle Jitter
-
-
-
500
250
250
-
-
-
500
250
250
-
-
-
500
250
250
-
-
-
500
250
250
pS
pS
pS
2, 4
2, 4
2, 4
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07106 Rev. *A
12/26/2002
Page 7 of 25
CYPRESS [ CYPRESS ]
