Approved Product
C9827H
High Performance Pentium® 4 Clock Synthesizer
Pin Description (Cont.)
PIN
NAME
PWR
I/O
Description
53
CPU_STP#
VDD
I
CPU Clock Disable Input. When asserted low, CPU (0:2) clocks are
synchronously disabled in a high state and CPU/(0:2) clocks are
synchronously disabled in a low state.
PU
24
66IN/3V66_5
VDD
VDD
I/O
O
Input connection for 66CLK(0:2) output clock buffers if S2 = 1, or
output clock for fixed 66 MHz clock if S2=0. See table on page 1
3.3 volt clock outputs. These clocks are buffered copies of the 66IN
clock or fixed at 66 MHz. See table on page 1
21, 22, 23
66B(0:2)/
3V66(2:4)
VDD
1, 8, 14, 19,
32, 37, 46, 50
4, 9, 15, 20,
27, 31, 36, 47
41
PWR 3.3V Power Supply
VSS
PWR Common Ground
VSSIREF
PWR Current reference programming input for CPU buffers. A resistor is
connected between this pin and IREF. See CPU Clock current Select
Table in page 18 of this data sheet. This pin should also be returned to
device VSS.
26
VDDA
-
PWR Analog power input. Used for PLL and internal analog circuits. Is also
specifically used to detect and determine when power is at an
acceptable level to enable the device to operate.
PU = Internal Pull-Up. PD = Internal Pull-Down. T = Tri level logic input with valid logic voltages of LOW=<0.8V, T=1.0-1.8V and
HIGH=>2.0V
2-Wire SMBus Control Interface
The 2-wire control interface implements a read/write slave only interface according to SMBus specification. (See
Application Note AN-0022).
The device will accept data written to the D2 address and data may read back from address D3. It will not respond to
any other addresses, and previously set control registers are retained as long as power in maintained on the device.
Serial Control Registers
Following the acknowledge of the Address Byte, two additional bytes must be sent:
1) “Command Code “ byte, and
2) “Byte Count” byte.
Although the data (bits) in the command is considered “don’t care”; it must be sent and will be acknowledged.
After the Command Code and the Byte Count have been acknowledged, the sequence (Byte 0, Byte 1, and Byte 2)
described below will be valid and acknowledged.
Note: The Pin# column lists the relevant pin number where applicable. The @Pup column gives the default state at
power up.
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07106 Rev. *A
12/26/2002
Page 3 of 25
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