Approved Product
C9827H
High Performance Pentium® 4 Clock Synthesizer
AC Parameters (Cont.)
66 MHz
100 MHz
133 MHz
200 MHz
Symbol
Parameter
Units
Notes
Min
Max
Min
Max
Min
Max
Min
Max
TDC
66B(0:2) Duty
Cycle
66B(0:2) rise and
fall times
Any 66B to any
66B Skew
66IN to 66B(0:2)
propagation delay
66B(0:2) Cycle to
Cycle Jitter
45
0.5
-
55
45
0.5
-
55
45
0.5
-
55
45
55
%
2, 4
Tr / Tf
TSKEW
Tpd
2.0
175
4.5
2.0
175
4.5
2.0
175
4.5
0.5
2.0
175
4.5
nS
pS
nS
pS
2, 3
2, 4
2.5
-
2.5
-
2.5
-
2.5
-
2, 4
TCCJ
100
100
100
100
2, 4, 18
TDC
TPeriod
THIGH
TLOW
Tr / Tf
PCI_F(0:2) PCI
(0:6) Duty Cycle
PCI_F(0:2) PCI
(0:6) period
PCI_F(0:2) PCI
(0:6) high time
PCI_F(0:2) PCI
(0:6) low time
PCI_F(0:2) PCI
(0:6) rise and fall
times
45
55
45
55
45
55
45
30
55
%
2, 4
1, 2, 4
19
30.0
12.0
12.0
0.5
-
-
30.0
12.0
12.0
0.5
-
-
30.0
12.0
12.0
0.5
-
-
-
-
nS
nS
nS
nS
12.0
12.0
0.5
-
-
-
-
20
2.0
2.0
2.0
2.0
3
TSKEW
TCCJ
Any PCI clock to
Any PCI clock
Skew
PCI_F(0:2) PCI
(0:6) Cycle to
Cycle Jitter
-
-
500
250
-
-
500
250
-
-
500
250
-
-
500
250
pS
pS
2, 4
2, 4
TDC
USB48M Duty
Cycle
45
55
45
55
45
55
45
55
%
2, 4
TPeriod
Tr / Tf
USB48M period
USB48M rise and
fall times
20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 20.8299 20.8333
nS
nS
2, 4
2, 3
1.0
2.0
1.0
2.0
1.0
2.0
1.0
2.10
TCCJ
TDC
USB48M Cycle to
Cycle Jitter
-
350
-
350
-
350
-
350
pS
%
1, 2, 4
2, 4
DOT48 Duty
Cycle
45
55
45
55
45
55
45
55
TPeriod
Tr / Tf
DOT48 period
DOT48 rise and
fall times
20.837
0.5
20.837
0.5
20.837
0.5
20.837
0.5
nS
nS
2, 4
2, 4
1.0
1.0
1.0
1.0
TCCJ
DOT48Cycle to
Cycle Jitter
-
350
-
350
-
350
-
350
pS
2, 4
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07106 Rev. *A
12/26/2002
Page 8 of 25
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