C9821
Direct Rambus Plus Clock Generator
Preliminary
State Transitions
The clock source has three fundamental operating states. Figure 5 shows the state diagram with each transition
labeled A through J. Note that the clock source output need NOT be glitch-free during state transitions.
Vdd turn-on
G
J
Normal
F
B
A
E
D
C
Vdd turn-on
Vdd turn-on
H
Powerdown
Clk Stop
Figure 5: Clock Source State Diagram
Upon powering up the device, the device can enter any state, depending on the settings of the control signals
PwrDnB and StopB.
In Powerdown mode, the clock source is powered down with the control signal, PwrDnB, equal to 0. The control
signals S0, S1, and S2 must be stable before power is applied to the device, and can only be changed in
Powerdown mode (PwrDnB=0). The reference inputs, VddIR and VddIPd, may remain on or may be grounded
during the Powerdown mode.
The control signals Mult0, Mult1 can be used in two ways. If they are changed during Powerdown mode, then the
Powerdown transition timings determine the settling time of the DRCG. However, the Mult0 and Mult1 control signals
can also be changed during Normal mode. When the Mult control signals are “hot swapped” in this manner, the Mult
transition timings determine the settling time of the DRCG.
In Clk Stop mode, the clock source is on, but the output is disabled (StopB de-asserted). The VddIPD reference input
may remain on or may be grounded during the Clk Stop mode. The VddIR reference input must remain on during the
Clk Stop mode.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.1
9/7/1999
Page 8 of 17
CYPRESS [ CYPRESS ]
