C9821
Direct Rambus Plus Clock Generator
Preliminary
Table of Frequencies and Gear Ratios (Cont.)
Pclk
67
100
100
133
Refclk
33
50
50
67
Busclk
267
300
400
400
Synclk
67
75
100
100
A
8
6
8
6
B
1
1
1
1
M
2
4
4
4
N
2
3
4
3
Ratio
1.0
1.33
1.0
F@PD
33
25
25
33
1.33
Table 1A. Frequencies, Dividers, and Gear Ratios
A: Feedback divider in the DRCG PLL.
B: Refclk divider in the DRCG PLL
M: Pclk divider in the gear ratio logic.
N: synclk divider in the gear ratio logic.
Table 1A above shows several supported Pclk and Busclk frequencies, the corresponding A and B dividers required
in the DRCG PLL, and the corresponding M and N dividers in the gear ratio logic. The column Ratio gives the Gear
Ratio as defined by Pclk/Synclk (same as M/N). The column F@PD gives the divided down frequency (in MHz) at
the Phase Detector, where F@PD = Pclk/M = Synclk/N.
Table 1B below show examples of CLK/CLKB frequencies for different DRCG input frequencies.
Mult0
Mult1
DRCG input Frequency
CLK and CLKB
output frequency
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
50 MHz
50 MHz
50 MHz
50 MHz
66 MHz
66 MHz
66 MHz
66 MHz
225 MHz
300 MHz
267 MHz
400 MHz
300 MHz
400 MHz
356 MHz
533 MHz
Table 1B: CLK and CLKB example frequencies
Selection Logic
Mult0
Mult1
A
9
B
0
0
1
1
0
1
0
1
2
1
3
1
6
16
8
Table 2: PLL Divider Selection
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.1
9/7/1999
Page 5 of 17
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