C9821
Direct Rambus Plus Clock Generator
Preliminary
Mult Transition Timing Diagram
Mult0 and/
or Mult1
tMULT
Clk/ClkB
Figure: 8
Transition Specifications
Transition Latency
(target spec)
Transition
From
To
Description
Symbol
Max
A
C
G
H
J
Powerdown
Powerdown
Vdd on
Normal
Clk Stop
Normal
Clk Stop
Normal
Normal
Normal
tPOWERUP
3 ms
3 ms
3 ms
3 ms
1 ms
10 ns
20
Time from PwrDnB to Clk/ClkB output settled
(excluding tDISTLOCK).
Time from PwrDnB to when the internal PLL
and clock has turned on and settled.
Time from Vdd is applied and settled to Clk/ClkB
output settled (excluding tDISTLOCK).
Time from Vdd is applied and settled to the
internal PLL and clock has turned on and settled.
Time from Mult0 or Mult1 change to Clk/ClkB
output re-settled (excluding tDISTLOCK).
Time from StopB to when Clk/ClkB provides
glitch-free clock edges.
tPOWERUP
tPOWERUP
tPOWERUP
tMULT
Vdd on
Normal
E
E
Clk Stop
Clk Stop
tCLKON
tCLKSETL
Time from stopB to Clk/ClkB output settled to
cycles within 50 ps of the phase before StopB was
disabled.
F
B,D
Normal
Normal or
Clk Stop
Clk Stop
Powerdown
tCLKOFF
tPOWERDN
5 ns
1ms
Time from StopB to Clk/BlkB output disabled.
Time from PwerDnB to the device in
Powerdown.
Table 7: State Transition Latency Specifications
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.1
9/7/1999
Page 10 of 17
CYPRESS [ CYPRESS ]
