C9821
Direct Rambus Plus Clock Generator
Preliminary
AC Operating Conditions
Characteristic
Symbol
tCYCLE,IN
Min Typ Max
Units
Refclk Input Cycle Time
10
6a
-
-
-
-
-
-
-
-
-
40
40
nS
nS
Faster speed bin for Refclk input cycle timea
Input Cycle-to-cycle jitterb
tJ,IN
-
250
60%
33
pS
c
Input Duty Cycle over 10,000 cycles
Input Frequency of Modulation
DCIN
40%
30
-
tCYCLE
kHz
%
C
fMIN,IN
c
Modulation index for triangular modulation
Modulation index for non-triangular modulation
Phase Detector Input Cycle time at PclkM and SynclkN
PM,IN
0.6
0.5d
100
0.5
-
%
tCYCLE, PD
tERR,INIT
30
-0.5
nS
Initial Phase Error at Phase Detector Inputs (required
range of phase aligner)
tCYCLE,PD
Phase Detector Input Duty Cycle over 10,000 Cycles
DCIN,PD
tI,SR
25%
1
-
-
75%
4
tCYCLE,PD
V/nS
Input Slew Rate (measured at 20% - 80% of input
voltage) for PclkM, SynclkN, and Refclk
Input Capacitance at PclkM, SynclkN, and Refclke
Input Capacitance Matching at PclkM and SynclkNe
CIN,PD
∆CIN,PD
CIN,CMOS
-
-
-
-
-
-
7
pF
pF
pF
0.5
10
Input Capacitance at Scalable CMOS Pins (excluding
PclkM, SynclkN, and Refclk)e
a. Faster speed bin for future systems (not a requirement now), and applicable for VDDI,R>1.7V only
b. Refclk jitter measured at VDDI,R(nom)/2
c. If input modulation is used, input modulation is allowed but not required.
d. The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream
tracking skew, which cannot exceed the skew generated by the specified 0.6% triangular modulation. Typically, the
amount of allowed non-triangular modulation is about 0.5%.
e. Capacitance measured at Freq = 1 MHz, DC bias = 0.9V, and VAC<100mV
Table 12: AC Operating Conditions
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.1
9/7/1999
Page 14 of 17
CYPRESS [ CYPRESS ]
