+/+…when timing is critical
C9819
133 MHz I2C Clock Generator for Mobile Pentium®III / Rambus Systems
Preliminary
Group Limits and Parameter (applicable to all settings: Sel133/100# = x)
Symbol Parameter
Min Typ
Max
55
Units
%
Notes
TDC
Duty Cycle
45
0
50
-
6, 8, 9
6, 8, 9
6, 8, 9
6, 8, 9
6, 8, 9
Toff1
Toff2
Toff4
Toff5
CPU to 3V66-(0:2) offset, CPU leads
3V66-(0:2) to PCI(_F,0:6) offset, 3V66 leads
CPU to IOAPIC(0:1) offset, CPU leads
CPU to CPU/2 offset, CPU leads
1.5
3.5
4.0
3.5
nS
1.0
1.5
0.5
-
nS
-
nS
-
nS
Note 5: This parameter is measured as an average over 1uS duration, with a crystal center frequency of 14.31818MHz
Note 6: All outputs loaded as per table 6 below.
Note 7: Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V and 2.0V for
2.5V signals (see Fig.7A and Fig.7B)
Note 8: Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals and at 1.25V for 2.5V signals. (see Figs.7A & 7B)
Note 9: This measurement is applicable with Spread ON or Spread OFF.
Note 10: Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals, (see Figs. 7A & 7B)
Note 11: Probes are placed on the pins, and measurements are acquired at 0.4V.
Note 12: The time specified is measured from when all VDD’s reach their respective supply rail (3.3V and 2.5V) till the frequency output is stable
and operating within the specifications
Note 13: As this function is available through I2C only, therefore, the time specified is guaranteed by design.
Note 14: CPU_STP# and PCI_STP# setup time with respect to any PCI_F clock to guarantee that the effected clock will stop or start at the next
PCI_F clock’s rising edge.
Output Name
Max Load (in pF)
CPU, IOAPIC(0:1), CPU/2
PCI(_F,0:6), 3V66(0:2)
48 MHz , REF(0:2)
20
30
20
Table 6.
INTERNATIONAL MICROCIRCUITS, INC 525 LOS COCHES ST.
MILPITAS, CA 95035, USA TEL: 408-263-6300 FAX 408-263-6571
Rev 1.0
11/1/1999
Page 12 of 17
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