+/+…when timing is critical
C9819
133 MHz I2C Clock Generator for Mobile Pentium®III / Rambus Systems
Preliminary
AC Parameters
133 MHz Host
100 MHz Host
Symbol
Parameter
Units
Notes
5, 6, 8
6,10
6, 11
6, 7
6, 8, 9
Min
7.5
1.87
1.67
0.4
-
Max
8.0
-
Min
10.0
3.0
2.8
0.4
-
Max
10.5
-
TPeriod
THIGH
TLOW
Tr / Tf
CPU period
CPU high time
CPU low time
nS
nS
nS
nS
pS
-
-
CPU rise and fall times
CPU Cycle to Cycle Jitter
1.6
250
1.6
250
TCCJ
TPeriod
THIGH
TLOW
Tr / Tf
TCCJ
CPU/2 period
CPU/2 high time
CPU/2 low time
CPU/2 rise and fall times
CPU/2 Cycle to Cycle Jitter
15.0
5.25
5.05
0.4
-
16.0
-
-
1.6
250
20.0
7.5
7.3
0.4
-
21.0
-
-
1.6
250
nS
nS
nS
nS
pS
5, 6, 8
6,10
6, 11
6, 7
6, 8, 9
TPeriod
THIGH
TLOW
Tr / Tf
TSKEW
TCCJ
IOAPIC(0:1) period
IOAPIC(0:1) high time
IOAPIC(0:1) low time
IOAPIC(0:1) rise and fall times
IOAPIC0 to APIC1 Skew time
IOAPIC(0:1) Cycle to Cycle Jitter
60.0
25.5
25.3
0.4
-
-
-
-
60.0
25.5
25.3
0.4
-
-
-
nS
nS
nS
nS
pS
pS
5, 6, 8
6,10
6, 11
6, 7
6, 8, 9
6, 8, 9
N/S
1.6
250
500
1.6
250
500
-
-
TPeriod
THIGH
TLOW
Tr / Tf
TSKEW
TCCJ
3V66-(0:2) period
3V66-(0:2) high time
3V66-(0:2) low time
3V66-(0:2) rise and fall times
(Any 3V66 clock) to (Any 3V66 clock) Skew time
3V66-(0:2) Cycle to Cycle Jitter
15.0
5.25
5.05
0.4
-
16.0
-
-
1.6
250
500
15.0
5.25
5.05
0.4
-
16.0
-
-
1.6
250
500
nS
nS
nS
nS
pS
pS
5, 6, 8
6,10
6, 11
6, 7
6, 8, 9
6, 8, 9
-
-
TPeriod
THIGH
TLOW
Tr / Tf
TSKEW
TCCJ
PCI(_F,0:6) period
PCI(_F,0:6) period
PCI(_F,0:6) low time
PCI(_F,0:6) rise and fall times
(Any PCI clock) to (Any PCI clock) Skew time
PCI(_F,0:6) Cycle to Cycle Jitter
30.0
12.0
12.0
0.5
-
-
-
-
30.0
12.0
12.0
0.5
-
-
-
-
nS
nS
nS
nS
pS
pS
5, 6, 8
6,10
6, 11
6, 7
6, 8, 9
6, 8, 9
2.0
500
500
2.0
500
500
-
-
TPeriod
Tr / Tf
TCCJ
48MHz period ( conforms to +167ppm max)
48MHz rise and fall times
48MHz Cycle to Cycle Jitter
20.8299 20.8333 20.8299 20.8333
nS
nS
pS
5, 6, 8
6, 7
6, 8, 9
1.0
-
4.0
500
1.0
-
4.0
500
TPeriod
Tr / Tf
TCCJ
REF(0:2) period
REF(0:2) rise and fall times
REF(0:2) Cycle to Cycle Jitter
69.8413
1.0
-
71.0
4.0
1000
69.8413
1.0
-
71.0
4.0
1000
nS
nS
pS
5, 6, 8
6, 7
6, 8
tpZL, tpZH
tpLZ, tpZH
tstable
Output enable delay (all outputs)
Output disable delay (all outputs)
All clock Stabilization from power-up
Stopclock Set Up Time
1.0
1.0
10.0
10.0
3
1.0
1.0
10.0
10.0
3
nS
nS
mS
nS
13
13
12
14
tss
10.0
-
-
-
INTERNATIONAL MICROCIRCUITS, INC 525 LOS COCHES ST.
MILPITAS, CA 95035, USA TEL: 408-263-6300 FAX 408-263-6571
Rev 1.0
11/1/1999
Page 11 of 17
http://www.imicorp.com
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