C9707
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Preliminary
Strapping Resistor Options for pins with internal
Pull-downs:
The power up bi-directional pins have a large value pull-
down (50KΩ+/−20KΩ), therefore, a selection “0” is the
default. If the system uses a slow power supply (over
10mS settling time), then
it is recommended
to use an
external Pull-down (Rdn) in order to insure a low
selection. In this case, the designer may choose one of
two configurations, see Fig.6A and B.
Fig. 4A represents an additional pull down resistor 5KΩ
connected from the pin to the power line, which allows a
faster down to a high level.
If a selection “1” is desired, then a jumper is placed on
JP1 to a 1 KΩ resistor as shown in Fig.5A. Please note
the selection resistors (Rup and Rdn) are placed before
the Damping resistor (Rd) close to the pin.
Fig. 4B represent a single resistor 5KΩ connected to a
3-way jumper, JP2. When a “1” selection is desired, a
jumper is placed between leads1 and 3. When a “0”
selection is desired, a jumper is placed between leads 1
and 2.
V dd
IM I C 9 7 0 7
B id ire c tio n a l
R up
1K
Rd
Load
JP 1
JU M P E R
F ig . 4 A
R dn
5K
V dd
JP 2
3 W ay Jum per
3
2
1
R sel
5K
IM I C 9 7 0 7
B id ire c tio n a l
Rd
Load
F ig . 4 B
Power Management Functions
Power Management on this device is controlled by CPU_STP#, pin2.
When CPU_STP# is forced low, all CPU signals are synchronously (no glitch) disabled to a low state and CPU# signal is
in tristate. The CPU_STP# signal does not directly gate the CPU clocks, the CPU clocks will toggle one to three
complete cycles before stopping on a falling edge. When CPU_STP# is released to high, the CPU clocks are
synchronously re-enabled. The clocks will wait the equivalent of one to three cycles after CPU_STP# is asserted high
then will start toggling on the rising edge.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
http://www.imicorp.com
Rev 1.2
4/25/2000
Page 4 of 17
CYPRESS [ CYPRESS SEMICONDUCTOR ]
