C9707
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Preliminary
Product Features
•
•
•
•
•
•
•
•
•
•
•
1 differential pair and 1 single ended open drain
CPU clocks
6 PCI clocks
2 REF (3.3V) clocks at 14.318 MHz
1 48 MHz (3.3V), and one 24/48 MHz clock
System reset with watch dog feature
13 SDRAM clocks for 3 DIMMs
IMI Spread Spectrum for best EMI reduction
8 Spread Spectrum settings for each frequency
48 Pin SSOP Package
2
I C clock control with readback capability
Fine resolution frequency programming via Dial-a-
™
Frequency function
Frequency Table
S3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
S2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
S1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
S0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Table 1
Product Description
The C9707 is a main clock synthesizer chip for VIA
VT8371 (KX133) chipset and AMD Athlon (K7) CPU
based systems. This device provides all clocks required
with spread spectrum for EMI reduction.
It also
2
includes a comprehensive I C control interface to permit
individual clock enable and spread controls via system
software.
CPU
133.3
75
100.2
66.8
79
110
115
120
133.3
83.3
100.2
66.8
124
129
138
143
PCI
33.3
37.5
33.3
33.4
39.5
36.7
38.3
30
33.3
27.7
33.3
33.4
31.0
32.3
34.5
35.8
Block Diagram
VDD
REF0/(CPU_STP#)
XIN
XOUT
Pin Configuration
VDD
REF0/(CPU_STP#)
VSS
XIN
XOUT
VDD
PCI0/MODE
PCI1/S1
VSS
PCI2
PCI3
PCI4
PCI5
VDD
SDRAMIN
VSS
SDRAM11
SDRAM10
VDDS
SDRAM9
SDRAM8
VSS
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF1/S0
VSS
CPU-OD
VSS
CPU#
CPU
VDD
SReset
SDRAM12
VSS
SDRAM0
SDRAM1
VDDS
SDRAM2
SDRAM3
VSS
SDRAM4
SDRAM5
VDDS
SDRAM6
SDRAM7
VDD
48MHz/S2
24_48MHz/S3
OSC
REF1/S0
CPU-OD
S0
PLL1
S3 S2 S1
Stop
Clock
control
CPU
CPU#
VDD
PCI0/MODE
PCI1/S1
PCI2
PCI3
PCI4
PCI5
SReset
VDD
SDATA
SCLK
I2C
Logic
System
Watch
Dog
PLL2
/2
48M/S2
24_48M/S3
VDDS
SDRAM(0:12)
SDRAMIN
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
http://www.imicorp.com
Rev 1.2
4/25/2000
Page 1 of 17
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