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C9707AY 参数 Datasheet PDF下载

C9707AY图片预览
型号: C9707AY
PDF下载: 下载PDF文件 查看货源
内容描述: [Processor Specific Clock Generator, CMOS, PDSO48, SSOP-48]
分类和应用: 光电二极管外围集成电路
文件页数/大小: 17 页 / 248 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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C9707
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Preliminary
2-Wire I
2
C Control Interface
The 2-wire control interface implements a read/write slave only interface according to Philips I C specification. (see fig6,
2
page 7) . The device can be read back by using standard I C command bytes. Sub-addressing is not supported, thus all
preceding bytes must be sent in order to change one of the control bytes. The 2-wire control interface allows each clock
output to be individually enabled or disabled. 100 Kbits/second (standard mode) data transfer is supported.
During normal data transfer, the SDATA signal only changes when the SCLK signal is low, and is stable when SCLK is
high. There are two exceptions to this. A high to low transition on SDATA while SCLK is high is used to indicate the
start of a data transfer cycle. A low to high transition on SDATA while SCLK is high indicates the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes, after which an “acknowledge” is generated. The first byte of a
transfer cycle is a 7-bit address with a Read/Write bit (R/W#) as the LSB. R/W# = 1 in read mode. R/W# = 0 in write
mode.
The device will respond to writes to 10 bytes (max) of data to address
D2
by generating the “acknowledge” (low) signal
on the SDATA wire following reception of each byte. If the device should be read then an address
D3
must be sent.
Data is transferred MSB first at a max rate of 100kbits/S.
The device will not respond to any other control interface conditions, and previously set control registers are retained.
2
IMI Device
Master Device
SDATA
MSB
LSB
ACK
ACK
BYTE COUNT
(Don't Care)
ACK
BYTE 0
(Valid)
ACK
BYTE N
(Valid)
ACK
1
1
0
1
0
0
1
0
COMMAND BYTE
(Don't Care)
SCLK
8
8
8
8
STOP CONDITION
START
IMI Device
Master Device
SDATA
MSB
LSB
Fig.7a (WRITE)
ACK BYTE COUNT
BYTE 0
ACK
(Valid)
(Valid)
ACK
(Valid)
BYTE1
ACK
BYTE N
NO ACK
(Valid)
1
1
0
1
0
0
1
1
SCLK
START CONDITION
8
8
8
8
STOP CONDITION
Fig.7b (READ)
Figure 7
I C Communications Waveforms
2
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
http://www.imicorp.com
Rev 1.2
4/25/2000
Page 7 of 17