BCM88335 Data Sheet
I2S Interface
Table 10: UART Timing Specifications
Min.
Ref No. Characteristics
Typ.
Max.
Unit
1
2
3
Delay time, UART_CTS_N low to UART_TXD valid
–
–
–
–
–
–
1.5
0.5
0.5
Bit period
Bit period
Bit period
Setup time, UART_CTS_N high before midpoint of stop bit
Delay time, midpoint of stop bit to UART_RTS_N high
I2S Interface
2
2
The BCM88335 supports two independent I S digital audio ports. The I S signals are:
2
2
•
•
•
•
I S clock: I S SCK
2
2
I S Word Select: I S WS
2
2
I S Data Out: I S SDO
2
2
I S Data In: I S SDI
2
2
2
I S SCK and I S WS become outputs in master mode and inputs in slave mode, while I S SDO always stays
as an output. The channel word length is 16 bits and the data is justified so that the MSB of the left-channel data
2
2
is aligned with the MSB of the I S bus, per the I S specification. The MSB of each data word is transmitted one
bit clock cycle after the I S WS transition, synchronous with the falling edge of bit clock. Left-channel data is
transmitted when I S WS is low, and right-channel data is transmitted when I S WS is high. Data bits sent by
the BCM88335 are synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on
the rising edge of I2S_SSCK.
2
2
2
The clock rate in master mode is either of the following:
48 kHz x 32 bits per frame = 1.536 MHz
48 kHz x 50 bits per frame = 2.400 MHz
The master clock is generated from the input reference clock using a N/M clock divider.
In the slave mode, any clock rate is supported to a maximum of 3.072 MHz.
Broadcom®
September 23, 2015 • 88335-DS100-R
Page 50
BROADCOM CONFIDENTIAL
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