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BCM88335L2CUBG 参数 Datasheet PDF下载

BCM88335L2CUBG图片预览
型号: BCM88335L2CUBG
PDF下载: 下载PDF文件 查看货源
内容描述: [Telecom Circuit, 1-Func, PBGA145, WLBGA-145]
分类和应用: 电信电信集成电路
文件页数/大小: 140 页 / 2728 K
品牌: CYPRESS [ CYPRESS ]
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BCM88335 Data Sheet  
I2S Interface  
2
I S Timing  
Note: Timing values specified in Table 11 are relative to high and low threshold levels.  
Table 11: Timing for I2S Transmitters and Receivers  
Transmitter  
Lower LImit Upper Limit  
Receiver  
Lower Limit Upper Limit  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Notes  
a
Clock Period T  
T
T
tr  
r
Master Mode: Clock generated by transmitter or receiver  
b
b
HIGH t  
0.35T  
0.35T  
0.35T  
0.35T  
HC  
tr  
tr  
tr  
tr  
LOWt  
LC  
Slave Mode: Clock accepted by transmitter or receiver  
c
c
d
HIGH t  
0.35T  
0.35T  
0.35T  
0.35T  
HC  
LC  
tr  
tr  
tr  
tr  
LOW t  
Rise time t  
0.15T  
RC  
tr  
Transmitter  
Delay t  
e
d
0
0.8T  
dtr  
Hold time t  
htr  
Receiver  
f
f
Setup time t  
0.2T  
0
sr  
r
Hold time t  
hr  
a. The system clock period T must be greater than Ttr and Tr because both the transmitter and receiver have to be  
able to handle the data transfer rate.  
b. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space  
ratio. For this reason, tHC and tLC are specified with respect to T.  
c. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that  
they can detect the signal. So long as the minimum periods are greater than 0.35Tr, any clock that meets the  
requirements can be used.  
d. Because the delay (tdtr) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter driven  
by a slow clock edge can result in tdtr not exceeding tRC which means thtr becomes zero or negative. Therefore,  
the transmitter has to guarantee that thtr is greater than or equal to zero, so long as the clock rise-time tRC is not  
more than tRCmax, where tRCmax is not less than 0.15Ttr.  
e. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the  
clock signal and T, always giving the receiver sufficient setup time.  
f. The data setup and hold time must not be less than the specified receiver setup and hold time.  
Broadcom®  
September 23, 2015 • 88335-DS100-R  
Page 51  
BROADCOM CONFIDENTIAL  
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