PRELIMINARY
CYW54907
17.6.2 USB 2.0 Timing Diagrams
Figure 35 shows the important timing parameters associated with a post-reset transition to high-speed (HS) operation.
Figure 35. USB 2.0 Bus Reset to High-Speed Mode Operation
40 to 60 μs
< 100 μs
100 to 500 μs
DP
Idle
Idle
HS Data
High-
Speed
Chirp
Device
K-Chirp
DM
HS Data
3 to 3.125 ms
> 1.0 ms
100 to
875 μs
< 7 ms
> 10 ms
Start of Host
End of Host
(Hub) Chirp
End of
Reset
Device Goes
(Hub) Chirp
Start of
Reset
into Full-
Device Tests for
Single-Ended Zero
(SE0) State
Speed Mode
Figure 36 shows the USB 2.0 HS Mode transmit timing.
Figure 36. USB 2.0 High-Speed Mode Transmit Timing
96 bits
Latency = 42 bits
DP/DM
CLK60
PID
B0
B1
TXDATA
TXVALID
TXREADY
XVERSEL
00
OPMODE
TERMSEL
00
0
TX driver is enabled here.
Document Number: 002-19312 Rev. *C
Page 88 of 95
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