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BCM43907KWBGT 参数 Datasheet PDF下载

BCM43907KWBGT图片预览
型号: BCM43907KWBGT
PDF下载: 下载PDF文件 查看货源
内容描述: [WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor]
分类和应用:
文件页数/大小: 128 页 / 2500 K
品牌: CYPRESS [ CYPRESS ]
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BCM43907 Preliminary Data Sheet  
Signal Descriptions  
Table 10: Signal Descriptions (Cont.)  
Signal Name Type Description  
Bump Number  
Hibernation Block, Power-Down/Power-Up, and Reset  
100  
REG_ON  
I
Used by PMU to power up or power down the internal  
BCM43907 regulators used by the WLAN and APP  
sections. Also, when deasserted, this pin holds the WLAN  
and APP sections in reset. This pin has an internal 200 kΩ  
pull-down resistor that is enabled by default. It can be  
disabled through programming.  
282  
HIB_REG_ON_IN  
I
Used by the hibernation block to power up or power down  
the internal BCM43907 regulators. For applications that  
use the hibernation block, HIB_REG_ON_OUT must  
connect to REG_ON. Also, when deasserted, this pin  
holds the WLAN and APP sections in reset.  
278  
279  
283  
198  
HIB_REG_ON_OUT  
HIB_WAKE_B  
O
I
REG_ON output signal generated by the hibernation block.  
Wake up chip from hibernation mode.  
HIB_LPO_SELMODE  
SRSTN  
I
Select precise or coarse 32 kHz clock.  
I
System reset. This active-low signal resets the  
backplanes.  
I2S Interface  
153  
154  
163  
164  
I2S_MCLK0  
I2S_SCLK0  
I2S_LRCLK0  
I2S_SDATAI0  
I/O  
I/O  
I/O  
I
M clock  
S clock  
LR clock  
2
I S data input  
2
161  
I2S_SDATAO0  
O
I S data output  
158  
160  
162  
156  
I2S_MCLK1  
I2S_SCLK1  
I2S_LRCLK1  
I2S_SDATAI1  
I/O  
I/O  
I/O  
I
M clock  
S clock  
LR clock  
2
I S data input  
2
155  
I2S_SDATAO1  
O
I S data output  
JTAG Interface  
193  
JTAG_SEL  
I
JTAG select. This pin must be connected to ground if the  
JTAG interface is not used.  
No Connects  
1–5, 7–13,  
NO_CONNECT  
No connect  
16–20, 23, 24,  
26–34, 36–38,  
41, 43–49, 51,  
54, 55, 61–70, 179–  
181  
Broadcom®  
March 12, 2016 • 43907-DS104-R  
Page 61  
BROADCOM CONFIDENTIAL  
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