BCM43907 Preliminary Data Sheet
Signal Descriptions
Table 10: Signal Descriptions (Cont.)
Signal Name Type Description
Bump Number
SPI Interfaces
Note: Each SPI interface can alternatively be configured and used as a BSC interface.
76
78
81
82
83
84
86
80
SPI0_CLK
SPI0_MISO
SPI0_SISO
SPI0_CS
O
I
SPI clock
SPI data master in
SPI data master out
SPI slave select
SPI clock
O
O
O
I
SPI1_CLK
SPI1_MISO
SPI1_SISO
SPI1_CS
SPI data master in
SPI data master out
SPI slave select
O
O
UART Interface
85
91
88
87
UART0_CTS
UART0_RTS
UART0_RXD
UART0_TXD
I
UART clear-to-send
UART request-to-send
UART serial input
O
I
O
UART serial output
USB 2.0
170
167
169
175
184
165
USB2_DM
I/O
I/O
I
USB 2.0 data
USB2_DP
USB 2.0 data
USB2_RREF
USB2_MONCDR
USB2_MONPLL
USB2_DSEL
USB 2.0 reference resistor connection
USB 2.0 CDR monitor
O
O
I
USB 2.0 PLL monitor
USB 2.0 host and device mode selection
Voltage Regulators (Integrated)
108, 113, 122, 125 SR_VDDBAT5V
I
VBAT.
98, 99, 101, 102,
109, 112
SR_VLX
O
CBUCK switching regulator output
115, 116, 120, 127 LDO_VDD1P5
I
I
LNLDO input
128, 129
221
LDO_VDDBAT5V
LDO VBAT
WRF_XTAL_VDD1P35 I
XTAL LDO input (1.35V)
XTAL LDO output (1.2V)
Output of LNLDO
220
WRF_XTAL_VDD1P2
VOUT_LNLDO
O
106
O
O
O
O
O
O
114, 121, 126
118, 119
117
VOUT_CLDO
Output of core LDO
VOUT_3P3
LDO 3.3V output
VOUT_3P3_SENSE
VOUT_CLDO_SENSE
VOUT_BBPLLOUT
Voltage sense pin for LDO 3.3V output
Voltage sense pin for core LDO
Output of baseband PLL
103
107
Broadcom®
March 12, 2016 • 43907-DS104-R
Page 64
BROADCOM CONFIDENTIAL
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