ADVANCE
CYW43570
Figure 30 shows the WLAN boot sequence from power-up to firmware download.
Figure 30. WLAN Boot Sequence
VBAT*
VDDIO
WL_REG_ON
< 850 µs
VDDC
(from internal PMU)
< 104 ms
Internal POR
After a fixed delay following Internal POR and WL_REG_ON
< 4 ms
going high, the device responds to host F0 (address 0x14)
reads.
Device requests for reference clock
8 ms
After 8 ms the reference clock is
assumed to be up. Access to PLL
registers is possible.
Host Interaction:
Host polls F0 (address 0x14) until it reads a
predefined pattern.
Host sets wake-up-wlan bit and
waits 8 ms, the maximum time
for reference clock availability.
After 8 ms, host programs PLL
registers to set crystal frequency
Chip active interrupt is asserted after the PLL locks
Host downloads
code.**
*Notes:
1. VBAT should not rise 10%–90% faster than 40 microseconds.
2. VBAT should be up before or at the same time as VDDIO . VDDIO should NOT be present first or be held high
before VBAT is high.
3. For timing information of the host interaction (after asserting WL_REG_ON) to be ready for firmware download is
typically 124 ms, including POR.
4. Wi-Fi FW download depends on the system performance and memory available . Typically, the firmware download
on a FC19 Linux PC is 102 ms.
**Note:
1. Host download code is typically ~102 ms, but it also depends on the size of the firmware. After the firmware
download is complete, it is recommended to wait an additional 250 ms before host can issue control commands to a
dongle.
Document Number: 002-15054 Rev. *I
Page 86 of 94
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