ADVANCE
CYW43570
Figure 3. Power Topology (Typical)
CYW43570
BT_REG_ON
WL_REG_ON
VBAT
Internal
1.2V
WL RF — AFE
LNLDO
Core Buck
Regulator
CBUCK
Internal
1.2V
WL RF — TX (2.4 GHz & 5 GHz)
LNLDO
Internal
1.2V
WL RF — LO GEN (2.4 GHz & 5 GHz)
WL RF — RX/LNA (2.4 GHz & 5 GHz)
VCOLDO
Internal
1.2V
LNLDO
1.2V
XTAL LDO
WL RF — XTAL
WL RF — RFPLL PFD/MMD
BT RF/FM
1.35v
LNLDO
1.2V
(Max. 150 mA)
DFE/DFLL
PCIE PLL/RXTX
WLAN BBPLL/DFLL
WLAN/BT/CLB/Top, always ON
WL OTP
1.1V
CLDO
1.2-
VDDIO
(Max. 300 mA)
1.1V
LPLDO1
(Bypass in deep sleep)
WL PHY
WL DIGITAL
BT DIGITAL
WL/BT SRAMs
BT CLASS 1 PA
BTLDO2P5
2.5V
(Max. 70 mA)
WL RF — PA (2.4 GHz & 5 GHz)
WL PAD (2.4 GHz & 5 GHz)
VDDIO_RF
WL OTP (3.3V)
Internal
LNLDO
2.5v
2.5v
WL RF—VCO
WL RF—CP
Internal
LNLDO
Document Number: 002-15054 Rev. *I
Page 10 of 94
CYPRESS [ CYPRESS ]
