ADVANCE
CYW43570
Figure 2. CYW43570 Block Diagram
CYW43570
USB 2.0
WLAN
Debug
ARMCR4
AHB
Bluetooth
PMU
Controller
SW REG
LDO
Power Supply
LPO
XTAL OSC
POR
XTAL
RAM
ROM
WL REG ON
AHB2 APB
Bridge
APB
Patch
WD Timer
SW Timer
GPIO Ctrl
Inter Ctrl
DMA
ARM
GPIO
GPIO
PCIe
OTP
GPIO
WLAN HOST WAKE
PCIe
Bus Arb
PTU
UART
USB
I2S
AHB
RAM
ROM
PA
BT RF
BT PHY
PCM
5 GHz iPA
CLB
BT HOST WAKE
BT DEV WAKE
LNA
LNA
2.4 GHz iPA
Diplexer
3DG VSYNC IN
BT Digital IO
3DG VSYNC OUT
GPIO
LNA
5 GHz iPA
SMPS Control
BT Control Clock
Sleep
Clock
PMU
Controller
PMU
Timer Management
LNA
2.4 GHz iPA
Diplexer
BT‐WLAN ECI
XO
LPO
POR
Buffer
LNA
BT
EXT LNA RF Switch Control
XTAL
VBAT* VREG
BT REG ON
Note*: VBAT is the main power supply (ranges from 3.0V to 3.6V) to the chip.
Document Number: 002-15054 Rev. *I
Page 6 of 94
CYPRESS [ CYPRESS ]
