BCM43455 Preliminary Data Sheet
WLAN GPIO Signals and Strapping Options
WLAN GPIO Signals and Strapping Options
This section describes WLAN GPIO signals and strapping options. The pins are sampled at power-on reset
(POR) to determine the various operating modes. Sampling occurs a few milliseconds after an internal POR or
deassertion of the external POR. After the POR, each pin assumes the GPIO or alternative function specified
in the signal descriptions table. Each strapping option pin has an internal pull-up (PU) or pull-down (PD) resistor
that determines the default mode. To change the mode, connect an external PU resistor to VDDIO or a PD
resistor to GND, using a 10 kΩ resistor or less.
Note: Refer to the reference board schematics for more information.
Table 20: Strapping Options
Default Internal
WLBGA
Ball
Pull During
Strap
Pin Name Strap
Description
GPIO_7
sdio_padvddio
E1
1
Default pull = 1.
SDIO interface voltage.
1 = 1.8V,
0 = 3.3V.
Default is 1.8V.
GPIO_16 host_iface_sdio
K6
0
Default is PCIe. Pull high during
POR to select SDIO.
Broadcom®
November 5, 2015 • 43455-DS109-R
Page 91
BROADCOM CONFIDENTIAL
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