CYW4343X
4. WLAN System Interfaces
4.1 SDIO v2.0
The CYW4343X WLAN section supports SDIO version 2.0. for both 1-bit (25 Mbps) and 4-bit modes (100 Mbps), as well as high
speed 4-bit mode (50 MHz clocks—200 Mbps). It has the ability to map the interrupt signal on a GPIO pin. This out-of-band interrupt
signal notifies the host when the WLAN device wants to turn on the SDIO interface. The ability to force control of the gated clocks
from within the WLAN chip is also provided.
SDIO mode is enabled using the strapping option pins. See Table 24 on page 86 for details.
Three functions are supported:
■
■
Function 0 standard SDIO function. The maximum block size is 32 bytes.
Function 1 backplane function to access the internal System-on-a-Chip (SoC) address space. The maximum block size is
64 bytes.
■
Function 2 WLAN function for efficient WLAN packet transfer through DMA. The maximum block size is 512 bytes.
4.1.1 SDIO Pin Descriptions
Table 5. SDIO Pin Descriptions
SD 1-Bit Mode
SD 4-Bit Mode
gSPI Mode
DATA0
DATA1
DATA2
DATA3
CLK
Data line 0
DATA
Data line
Interrupt
DO
IRQ
NC
Data output
Data line 1 or Interrupt
Data line 2
IRQ
NC
Interrupt
Not used
Card select
Clock
Not used
Not used
Clock
Data line 3
NC
CS
Clock
CLK
CMD
SCLK
DI
CMD
Command line
Command line
Data input
Figure 17. Signal Connections to SDIO Host (SD 4-Bit Mode)
CLK
CMD
CYW4343X
SD Host
DAT[3:0]
Figure 18. Signal Connections to SDIO Host (SD 1-Bit Mode)
CLK
CMD
CYW4343X
SD Host
DATA
IRQ
Document No. 002-14797 Rev. *H
Page 25 of 128
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