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BCM4343SKUBG 参数 Datasheet PDF下载

BCM4343SKUBG图片预览
型号: BCM4343SKUBG
PDF下载: 下载PDF文件 查看货源
内容描述: [Single-Chip IEEE 802.11 b/g/n MAC/ Baseband/Radio with Bluetooth 4.1,an FM Receiver, and Wireless Charging]
分类和应用: 无线
文件页数/大小: 127 页 / 10739 K
品牌: CYPRESS [ CYPRESS ]
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CYW4343X  
4.3.1 Command Structure  
The gSPI command structure is 32 bits. The bit positions and definitions are shown in Figure 22.  
Figure 22. gSPI Command Structure  
BCM_SPID Command Structure  
27  
31 30 29 28  
11 10  
0
C
A
F1 F0  
Address – 17 bits  
Packet length - 11bits *  
* 11’h0 = 2048 bytes  
Function No: 00 – Func 0: All SPI-specific registers  
01 – Func 1: Registers and memories belonging to other blocks in the chip (64 bytes max)  
10 – Func 2: DMA channel 1. WLAN packets up to 2048 bytes.  
11 – Func 3: DMA channel 2 (optional). Packets up to 2048 bytes.  
Access : 0 – Fixed address  
1 – Incremental address  
Command : 0 – Read  
1 – Write  
4.3.1.1 Write  
The host puts the first bit of the data onto the bus half a clock-cycle before the first active edge following the CS going low. The fol-  
lowing bits are clocked out on the falling edge of the gSPI clock. The device samples the data on the active edge.  
4.3.1.2 Write/Read  
The host reads on the rising edge of the clock requiring data from the device to be made available before the first rising-clock edge  
of the data. The last clock edge of the fixed delay word can be used to represent the first bit of the following data word. This allows  
data to be ready for the first clock edge without relying on asynchronous delays.  
4.3.1.3 Read  
The read command always follows a separate write to set up the WLAN device for a read. This command differs from the write/read  
command in the following respects: a) chip selects go high between the command/address and the data, and b) the time interval  
between the command/address is not fixed.  
4.3.2 Status  
The gSPI interface supports status notification to the host after a read/write transaction. This status notification provides information  
about packet errors, protocol errors, available packets in the RX queue, etc. The status information helps reduce the number of inter-  
rupts to the host. The status-reporting feature can be switched off using a register bit, without any timing overhead. The gSPI bus  
timing for read/write transactions with and without status notification are as shown in Figure 23 below and Figure 24 on page 30.  
See Table 6 on page 30 for information on status-field details.  
Document No. 002-14797 Rev. *H  
Page 28 of 128  
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