欢迎访问ic37.com |
会员登录 免费注册
发布采购

BCM4343SKUBG 参数 Datasheet PDF下载

BCM4343SKUBG图片预览
型号: BCM4343SKUBG
PDF下载: 下载PDF文件 查看货源
内容描述: [Single-Chip IEEE 802.11 b/g/n MAC/ Baseband/Radio with Bluetooth 4.1,an FM Receiver, and Wireless Charging]
分类和应用: 无线
文件页数/大小: 127 页 / 10739 K
品牌: CYPRESS [ CYPRESS ]
 浏览型号BCM4343SKUBG的Datasheet PDF文件第19页浏览型号BCM4343SKUBG的Datasheet PDF文件第20页浏览型号BCM4343SKUBG的Datasheet PDF文件第21页浏览型号BCM4343SKUBG的Datasheet PDF文件第22页浏览型号BCM4343SKUBG的Datasheet PDF文件第24页浏览型号BCM4343SKUBG的Datasheet PDF文件第25页浏览型号BCM4343SKUBG的Datasheet PDF文件第26页浏览型号BCM4343SKUBG的Datasheet PDF文件第27页  
CYW4343X  
Figure 16. Recommended Circuit to Use with an External Dedicated TCXO  
200 pF – 1000 pF  
TCXO  
WLRF_XTAL_XOP  
WLRF_XTAL_XON  
NC  
Table 3. Crystal Oscillator and External Clock Requirements and Performance  
External Frequency  
Reference  
Crystal  
Min. Typ.  
Parameter  
Conditions/Notes  
Max.  
Min. Typ. Max.  
Units  
37.4a  
Frequency  
MHz  
Crystal load capacitance  
ESR  
12  
pF  
60  
Drive level  
External crystal must be able to tolerate 200  
this drive level.  
μW  
Input Impedance  
Resistive  
10k  
100k  
7
(WLRF_XTAL_XOP)  
Capacitive  
pF  
400b  
WLRF_XTAL_XOP input  
voltage  
AC-coupled analog signal  
1260  
mVp-p  
WLRF_XTAL_XOP input  
low level  
DC-coupled digital signal  
0
0.2  
V
WLRF_XTAL_XOP input  
high level  
DC-coupled digital signal  
1.0  
1.26  
20  
V
Frequency tolerance  
Initial + over temperature  
–20  
20  
–20  
ppm  
Duty cycle  
37.4 MHz clock  
40  
50  
60  
%
Phase Noisec, d, e  
(IEEE 802.11 b/g)  
37.4 MHz clock at 10 kHz offset  
37.4 MHz clock at 100 kHz offset  
37.4 MHz clock at 10 kHz offset  
37.4 MHz clock at 100 kHz offset  
37.4 MHz clock at 10 kHz offset  
37.4 MHz clock at 100 kHz offset  
–129  
–136  
–134  
–141  
–140  
–147  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
Phase Noisec, d, e  
(IEEE 802.11n, 2.4 GHz)  
Phase Noisec, d, e  
(256-QAM)  
a. The frequency step size is approximately 80 Hz. The CYW4343X does not auto-detect the reference clock frequency; the frequency is specified  
in the software and/or NVRAM file.  
b. To use 256-QAM, a 800 mV minimum voltage is required.  
c. For a clock reference other than 37.4 MHz, 20 × log10(f/37.4) dB should be added to the limits, where f = the reference clock frequency in MHz.  
d. Phase noise is assumed flat above 100 kHz.  
e. The CYW4343X supports a 26 MHz reference clock sharing option. See the phase noise requirement in the table.  
3.3 External 32.768 kHz Low-Power Oscillator  
The CYW4343X uses a secondary low-frequency sleep clock for low-power mode timing. Either the internal low-precision LPO or an  
external 32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz ± 30% over process,  
voltage, and temperature, which is adequate for some applications. However, one trade-off caused by this wide LPO tolerance is a  
small current consumption increase during power save mode that is incurred by the need to wake up earlier to avoid missing bea-  
cons.  
Document No. 002-14797 Rev. *H  
Page 23 of 128  
 复制成功!