PRELIMINARY
CYW43438
Long Frame Sync, Slave Mode
Figure 26. PCM Timing Diagram (Long Frame Sync, Slave Mode)
1
2
3
PCM_BCLK
4
5
PCM_SYNC
9
PCM_OUT
PCM_IN
Bit 0
Bit 0
HIGH IMPEDANCE
8
Bit 1
6
7
Bit 1
Table 12. PCM Interface Timing Specifications (Long Frame Sync, Slave Mode)
Ref No.
Characteristics
Minimum
Typical
Maximum
Unit
MHz
ns
1
PCM bit clock frequency
PCM bit clock low
PCM bit clock high
PCM_SYNC setup
PCM_SYNC hold
PCM_OUT delay
PCM_IN setup
–
41
41
8
–
–
–
–
–
–
–
–
12
–
2
3
4
5
6
7
8
–
ns
–
ns
8
–
ns
0
25
–
ns
8
ns
PCM_IN hold
8
–
ns
Delay from rising edge of PCM_BCLK during last bit period to
PCM_OUT becoming high impedance
9
0
–
25
ns
Document Number: 002-14796 Rev. *K
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