PRELIMINARY
CYW43438
10.1.6 PCM Interface Timing
Short Frame Sync, Master Mode
Figure 23. PCM Timing Diagram (Short Frame Sync, Master Mode)
1
2
3
PCM_BCLK
4
PCM_SYNC
PCM_OUT
8
High Impedance
7
5
6
PCM_IN
Table 9. PCM Interface Timing Specifications (Short Frame Sync, Master Mode)
Ref No.
Characteristics
Minimum
Typical
Maximum
Unit
MHz
ns
1
PCM bit clock frequency
PCM bit clock low
PCM bit clock high
PCM_SYNC delay
PCM_OUT delay
PCM_IN setup
–
41
41
0
–
–
–
–
–
–
–
12
–
2
3
4
5
6
7
–
ns
25
25
–
ns
0
ns
8
ns
PCM_IN hold
8
–
ns
Delay from rising edge of PCM_BCLK during last bit period to
PCM_OUT becoming high impedance
8
0
–
25
ns
Document Number: 002-14796 Rev. *K
Page 42 of 101
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