BCM4339 Preliminary Data Sheet
Signal Descriptions
Table 20: FCFBGA, WLBGA, and WLCSP Signal Descriptions (Cont.)
WLBGA
Ball#
FCFBGA
Ball#
WLCSP
Bump#
Signal Name
Type Description
WLAN GPIO Interface
Note: The GPIO signals can be multiplexed via software and the JTAG_SEL pin to behave as various specific
functions. See Table 28: “BCM4339 GPIO/SDIO Alternative Signal Functions,” on page 118 for additional
details.
B6
C6
D6
B5
C5
D5
C4
D4
H1
–
D9
C16
C8
A7
B5
A5
C7
B7
E8
–
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_14
GPIO_13
GPIO_15
I/O Programmable GPIO pins.
Note: These GPIO signals can
be configured by software: as
either inputs or outputs, to have
internal pull-ups or pull-downs
enabled or disabled, and to use
either a high or low polarity
upon assertion.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
–
–
–
–
–
–
–
A3
D8
D6
–
–
JTAG Interface
E5
C6
205
JTAG_SEL
I/O JTAG select. Pull high to select
the JTAG interface. If the JTAG
interface is not used, this pin
may be left floating or
connected to ground.
Note:SeeTable 28: “BCM4339
GPIO/SDIO Alternative Signal
Functions,” on page 118 for the
JTAG signal pins.
Clocks
H12
J12
B4
P19
R19
J7
138
142
39
WRF_XTAL_IN
WRF_XTAL_OUT
LPO_IN
I
O
I
XTAL oscillator input.
XTAL oscillator output.
External sleep clock input
(32.768 kHz).
H3
W3
56
CLK_REQ
O
Reference clock request
(shared by BT and WLAN).
FM Transceiver and SFLASH
–
–
N3
P3
49
46
BT_SF_MOSI
BT_SF_CLK
I/O SFLASH_SI
I/O SFLASH_CLK
Broadcom®
November 17, 2014 • 4339-DS106-R
Page 107
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