BCM4339 Preliminary Data Sheet
Signal Descriptions
Signal Descriptions
The signal name, type, and description of each pin in the BCM4339 is listed in Table 20. The symbols shown
under Type indicate pin directions (I/O = bidirectional, I = input, O = output) and the internal pull-up/pull-down
characteristics (PU = weak internal pull-up resistor and PD = weak internal pull-down resistor), if any.
Table 20: FCFBGA, WLBGA, and WLCSP Signal Descriptions
WLBGA
Ball#
FCFBGA
Ball#
WLCSP
Bump#
Signal Name
Type Description
WLAN and Bluetooth RF Signal Interface
N7
W10
118
WRF_RFIN_2G
I
2.4 GHz Bluetooth and WLAN
receiver shared input.
N5
W8
93
BT_RF_TX
O
I
Bluetooth PA output.
N12
N8
W18
W12
W16
V11
102
115
106
121
WRF_RFIN_5G
WRF_RFOUT_2G
WRF_RFOUT_5G
WRF_TSSI_A
5 GHz WLAN receiver input.
2.4 GHz WLAN PA output.
5 GHz WLAN PA output.
O
O
I
N11
J7
5 GHz TSSI input from an
optional external power
amplifier/power detector.
H7
V10
122
WRF_RES_EXT/
WRF_GPIO_OUT/
WRF_TSSI_G
I/O GPIO or 2.4 GHz TSSI input
from an optional external power
amplifier/power detector.
RF Switch Control Lines
F12
F11
E12
E11
D12
F8
J19
J17
J18
G19
H17
G17
G18
J16
G16
H16
145
146
147
148
149
150
151
152
153
154
RF_SW_CTRL_0
RF_SW_CTRL_1
RF_SW_CTRL_2
RF_SW_CTRL_3
RF_SW_CTRL_4
RF_SW_CTRL_5
RF_SW_CTRL_6
RF_SW_CTRL_7
RF_SW_CTRL_8
RF_SW_CTRL_9
O
O
O
O
O
O
O
O
O
O
Programmable RF switch
control lines. The control lines
are programmable via the
driver and NVRAM file.
H9
G7
E10
F5
WLAN PCI Express Interface
–
A19
–
PCIE_CLKREQ_L
OD PCIe clock request signal which
indicates when the REFCLK to
the PCIe interface can be
gated.
1 = the clock can be gated
0 = the clock is required
–
B16
–
PERST_L
I (PU) PCIe System Reset. This input
is the PCIe reset as defined in
the PCIe base specification
version 1.1.
Broadcom®
November 17, 2014 • 4339-DS106-R
Page 105
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