BCM4339 Preliminary Data Sheet
Signal Descriptions
Table 20: FCFBGA, WLBGA, and WLCSP Signal Descriptions (Cont.)
WLBGA
Ball#
FCFBGA
Ball#
WLCSP
Bump#
Signal Name
Type Description
–
–
–
–
B13
C13
A18
B18
–
–
–
–
PAD_RDN0
I
I
I
I
Receiver differential pair (x1
lane).
PAD_RDP0
PAD_REFCLKN
PAD_REFCLKP
PCIE Differential Clock inputs
(negative and positive). 100
MHz differential.
–
–
–
B15
B14
B19
–
–
–
PAD_TDN0
PAD_TDP0
PCI_PME_L
O
O
Transmitter differential pair (x1
lane).
OD PCI power management event
output. Used to request a
change in the device or system
power state. The assertion and
deassertion of this signal is
asynchronous to the PCIe
reference clock. This signal has
an open-drain output structure,
as per the PCI Bus Local Bus
Specification, revision 2.3.
–
–
–
–
–
–
PAD_TESTP
PAD_TESTN
–
–
PCIe test pin.
WLAN SDIO Bus Interface
Note: These signals can also have alternate functionality depending on package and host interface mode.
Refer to Table 28: “BCM4339 GPIO/SDIO Alternative Signal Functions,” on page 118 for additional details.
B11
B12
B10
C10
D10
C11
B11
C11
C10
A11
C9
171
172
173
174
175
176
SDIO_CLK
I
SDIO clock input.
SDIO_CMD
I/O SDIO command line.
I/O SDIO data line 0.
I/O SDIO data line 1.
I/O SDIO data line 2.
I/O SDIO data line 3.
SDIO_DATA_0
SDIO_DATA_1
SDIO_DATA_2
SDIO_DATA_3
B9
Broadcom®
November 17, 2014 • 4339-DS106-R
Page 106
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