BCM4330 Preliminary Data Sheet
WLAN Host Interfaces
Section 11: WLAN Host Interfaces
SDIO v2.0
The BCM4330 WLAN section supports SDIO version 2.0. for both 1-bit (25 Mbps), 4-bit modes (100 Mbps), and
high speed 4-bit (50 MHz clocks—200 Mbps). It has the ability to map the interrupt signal onto a GPIO pin. This
out-of-band interrupt signal notifies the host when the WLAN device wants to turn on the SDIO interface. The
ability to force control of the gated clocks from within the WLAN chip is also provided.
SDIO mode is enabled using the strapping option pins strap_host_ifc_[3:1] (Table 19: “WLAN GPIO Functions
and Strapping Options,” on page 112).
Three functions are supported:
• Function 0 Standard SDIO function (Max BlockSize/ByteCount = 32B)
• Function 1 Backplane Function to access the internal System On Chip (SOC) address space (Max BlockSize/
ByteCount = 64B)
• Function 2 WLAN Function for efficient WLAN packet transfer through DMA (Max BlockSize/ByteCount =
512B)
SDIO Pin Descriptions
Caution! The SDIO interface pins are not 3.3V tolerant. All SDIO signaling should be limited to
2.9V ±3%, 2.5V, 1.8V, or 1.2V, depending on the I/O power supply voltage VDDIO.
Table 14: SDIO Pin Description
SD 4-Bit Mode
SD 1-Bit Mode
DATA Data line
gSPI Mode
Data output
Interrupt
Not used
Card select
DATA0
DATA1
DATA2
DATA3
CLK
Data line 0
Data line 1 or Interrupt IRQ
Data line 2 or Read Wait RW
Data line 3
Clock
Command line
DO
IRQ
NC
CS
Interrupt
Read Wait
Not used
Clock
N/C
CLK
SCLK Clock
DI Data input
CMD
CMD Command line
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BCM4330 Preliminary Data Sheet
April 28, 2011 • 4330-DS304-RI
Page 74
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